US3241075A - Pulse regenerative devices - Google Patents
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- PCM Pulse Code Modulation
- each digit time slot contains one of the two figures: 1 characterized by the presence of a pulse or characterized by the absence of a pulse.
- This modulation system may be used for the transmission of voice frequency signals or telegraph signals and more generally for data transmission. It is well known that in such an operation the time positions of the pulses (called message signals) may be affected by certain fluctuations.
- the variations of the propagation conditions in the medium used to carry out the transmission introduce a variation of the repetition frequency of the message signals.
- These variations are called slow fluctuations and have a repetition frequency of about a few cycles per hour and a time period amplitude equal to a number of digit time slots.
- the crosstalk between the different transmission ways, noise in the propagation medium, induction effects due to industrial frequency alternating voltages, etc. introduce fast fluctuations or jitter on either side of the mean position of the message signals.
- the mean position of the message signals is where they would be found if they were affected only by slow fiuctuations.
- the repetition frequency of the fast fluctuations whose amplitude is relatively small may vary from a few cycles up to several tens of kilocycles per second.
- the jitter also interferes during the reshaping of the message signals in the regenerative device.
- the synchronization signals When the synchronization signals are obtained from pulses at the transmission point, they are aiiected by the same slow fluctuations that affect the message signal pulses themselves. When they are obtained from an independent clock placed in the repeater their frequency cannot remain identical to that of synchronization pulses obtained during transmission even though they are also affected by a slow drift.
- a new signal free of fluctuations is obtained.
- a coincidence circuit a signal derived from the message signal to a signal delivered by the local clock.
- a reshaped message signal is compared to a gate signal of a relatively long duration but shorter than the time interval separating the theoretical positions of two signals in adjacent digit time slots. If the message signal is inside the gate signal, the coincidence circuit delivers a signal which is afterwards placed in a well determined time position.
- a message signal may be lost either when it is placed in such a position that the gate signal does not exist, or when it coincides with one of the edges of the said signal, in which case an uncertainty exists in that the coincidence circuit may not operate if the overlapping of the two signals is not sufficient.
- the coincidence may take place on a time position adjacent to the exact time position to which the said signal belongs.
- the object of the present invention is therefore to suppress, in the regenerative devices, the errors due to low amplitude jitter superimposed on slow fluctuations of whatsoever amplitude which affects the time positions of pulses belonging to a group of code signals.
- FIGURE 1 shows a block diagram of an exemplary circuit made according to the invention
- FIGURE 2 shows the phase relation between the signals set into action in the circuit
- FIGURE 3 shows the signal appearing in several points of the circuit
- FIGURE 4 shows a sampling circuit used as an alternative circuit.
- FIGURE 1 is a diagrammatic representation of a means for achieving the desired results according to the invention.
- the message signal is received at the input of the regenerative device on conductor 10 and is applied to the circuit 101 for extraction of the input reference.
- This circuit comprises first a pulse shaping device of any well known type, delivering on output conductor 16 normalized pulses and second a circuit which delivers a sinusoidal reference signal having the same frequency as the repetition frequency of the pulses received on the conductor 10.
- this circuit may comprise a bandpass filter tuned to the nominal repetition frequency of the pulses received which, when energized by the normalized signals, delivers a sinusoidal signal on output conductor 11 of the circuit 101.
- This filter presents a relatively high surtension factor (high Q)
- a message signal gives rise toa certain number of cycles and the delivered signal may be considered as being permanent.
- This sinusoidal signal presents a constant phase relation with respect to the average position of the message signal so that it follows the slow fluctuation and it defines the time scale on which the received message signals are positioned.
- This sinusoidal signal is also affected by a certain amount of jitter.
- the jitter of the message signals and the jitter caused by the filter itself affects the sinusoidal signal. It has been found that the time period of this jitter is at most equal to a While the time period of the jitter of the message signal is equal at most to 1 both shown in FIG. 2.
- the normalized message signal delivered by the circuit 101 has a Width clearly lower than or and 'y.
- a local clock 102 is tuned to the nominal frequency of the synchronization signal used at the transmission and delivers a sinusoidal signal of same frequency on its output conductor 12 which is applied to one of the 3 inputs of the three phase discriminators 196, 1G7, 163 after the phase of the signal has been shifted respectively by 0, 21/3 and 41r/3 by the phase shifters 194 and 105'.
- the second input of each one of the discriminators receives the sinusoidal signal at the repetition frequency of the message signal transmitted over the conductor 11.
- Each discriminator delivers a signal only when the phase angle between the two signals applied to it does not exceed 21r/30t, so that the time period of its range of operation is 2TF/3Ot.
- the output of each one of the discriminators 1%, 1117 and 108 is connected respectively to the input referenced O of the bistable circuits or flipfiops 109, 1111 and 111. These circuits are connected together in a way such that the setting of one of them from the state to the 1 state, resets the two others in the 0 state.
- the output conductors 13, 14 and 15 referenced 1, of each one of the bistable circuits are respectively connected to one of the inputs of the AND circuits 112, 113, 114.
- the second input 16 of each one of these AND circuits receives from the circuit 101, the normalized message signals.
- the output conductors 17, 18, 19 of these AND circuits are connected to the retiming circuit 103, after passage, for the signals delivered by the AND circuits 113 and 112, through the delay circuits 115 and 116 which provide respectively delays corresponding to phase angles of 21r/ 3 and 41r/ 3.
- the retiming circuit 103 receives on its input conductor synchronization pulses delivered by the local clock 1(22.
- Each of the conductors 19 and 26 is connected to one input of a bistable flip-flop circuit 117.
- the signal appearing on conductor 19 sets the flip-flop in the 1 state, then, the signal appearing on conductor 20 resets it to the 0 state and delivers a pulse on the conductor 22, the time position of which is that of the synchronization signal 20.
- the signal is amplified in the circuit 119 and appears on output conductors 23.
- FIGURE 2a shows the duration of a repetition period of the synchronization signal delivered by the local clock 102 on the conductor 12 subdivided in to radians and degrees.
- the operational ranges of the discriminators and the phase angles between the different signals will be characterized by their angular value by taking for the positive phase direction, the direction OX corresponding to a time lag.
- the discriminator 106 which receives the signals present on conductors 11 and 12 delivers a signal when the phase angle between these two signals ranges between 0 and 27r/3oc. It is thus possible to draw, FIGURE 2b, the line segment of AB of length equal to 21r/3oc which represents the range of operation of the discriminator.
- the origin of which, A, is aligned with the beginning of the repetition period of signal 12 marked 0 (zero) on the FIGURE 2a.
- the signal delivered by this discriminator 106 is applied to the bistable circuit 1199 which sets to the 1 state, resetting at the same time the bistable circuits 119 and 111 which were in the 1 state.
- a signal appears on the output 13 of the bistable circuit 169 which activates the AND circuit 112.
- the discriminator 1116 does not deliver any signal and the bistable circuit 1&9 which remains in the 1 state still activates the AND circuit 112.
- the discriminator 1117 delivers a signal in its operation range A'B' which sets the fiip-fiop 1111 to the 1 state; consequently, the AND circuit 113 is activated.
- the AND circuit 114 is activated by the bistable circuit 111. It is seen therefore that the ranges of operation, AB, AB', A"B" of the three discriminators are separated by ranges of non operation A A, BA and BA of amplitude at the purpose of which is to prevent the jitter of the signal 11 from disturbing the bistables associated with it.
- the operation of the circuit takes place within the range BA, and the signal on conductor 11 is affected by a jitter of amplitude tit/2 on either side of its mean position. It is seen that whatever he the position of the signal in the range it can activate only one of the discriminators 1% or 107. Therefore with this exemplary circuit there could not be any cornmutations between the two adjacent bistable circuits 109 and due to the jitter of the sinusoidal signal on conductor 11. In short only one of the AND circuits 112, 113, 114 is activated for a given phase angle between the sinusoidal signals on conductors 11 and 12.
- the signal on conductor 16 is positioned with respect to the corresponding signal on conductor 11 so that its time position coincides with the beginning of a positive haif cycle of said signal on conductor 11, this being accomplished easily with a time delay circuit placed in the circuit 1111.
- FIGURE 20 shows a certain number of these normalized signals, 1, 2, 3, 4, 5 and 6 which occupy various time positions which will be always referenced With respect to the time scale of FIGURE 2a.
- the signal 1 of the FIGURE 20 occupies a time position equal to the time position of the associated signal on conductor 11 and therefore presents a phase angle less than 21r/3ot with respect to the signal on conductor 12.
- the discriminator 106 delivers, therefore, a signal to the flip-flop 109 which activates the input conductor 13 of the AND circuit 112.
- the message signal is applied on the second input conductor 16 of this AND circuit which thus delivers on its output conductor 17 and identical signal at the same time position 1.
- This signal undergoes a phase shift of 411'/ 3 in the circuit 116 before being applied to the input conductor 19 of the retiming circuit 103.
- FIGURE 2d shows in 1', the time position of this delayed signal. If this signal is affected by a jitter of maximum amplitude 'y, as shown hachured on FIGURE 20, this jitter is found once again on the conductor 19 on either side of the time position 1'.
- the discriminator 1126 delivers a signal. This signal 2 is thus found again, on the conductor 19, in the time position 2. If this signal is afiected by the jitter shown hachured, and if the signal 11 associated with it is placed at certain instants in the nonoperational range of the discriminators, nevertheless the bistable unit 109 keeps control and activates the AND circuit 112.
- the associated bistable circuit keeps the control of the AND circuit to which it is connected over a maximum phase angle of 21r/3+or of slow fluctuations.
- the circuit according to the invention comprises a fixed number, such as n, discriminators the control range of each one of the associated flip-flops is a phase angle of 21r/n+ut.
- a message signal whose associated sinusoidal signal is placed between the points on and 21r/ 3 is displaced by 41r/3 before being applied to the input 19 of the retiming circuit 1133. Its time position is thus placed, on this input 19, in a maximum range extending from i.e., in the range 47r/3Ot to 211'.
- a message signal whose associated sinusoidal signal is placed between the point 21r/ 3-nt and 41r/ 3 is displaced by 21r/3 and is also placed in the range 41r/30c to 21r.
- the time position of a message signal whose associated sinusoidal signal is placed between the points 41r/3a and Zn is not modified.
- the range occupied by the shifted message signals of the FIGURE 2d shall now be determined. Let us consider for instance the signal 9, FIGURE 26, whose associated sinusoidal signal is placed in the middle of the nonoperation range BA. If this position has been reached because of a slow fluctuation in the negative direction, it is the discriminator 167 which delivers a signal. In these conditions the signal 9 is carried back in 9', FIGURE 2d. If this position has been reached because of a slow fluctuation in the positive direction, it is the discriminator 106 which delivers a signal. The signal 9 is then placed in 9", FIGURE 2d.
- the jitter of these signals is shown hachured, and it is seen that, whatever the mean time position of a signal afiected by jitter and by slow fluctuations may be, the device, according to the invention, places it inside a range extending between 41r/3'y and Zr, it z; or inside a range extending between 41r/3-a and Zr, if Y OL In the course of the description, it will be assumed as a nonlimitative example that 'y ct.
- the retiming circuit 103 receives on its input conductor 20 signals delivered by the local clock 162 and on its input conductor 19 the message signals which, as seen previously, are placed inside time position ranges of duration 21r/it-I-7 such as shown on 7a and 7b, FIGURE 2e, and are still affected by their jitter.
- bistable circuit 117 the signal on conductor 19 being applied to the input 0 and the signal on conductor 20 to the input 1.
- the 1 output of this bistable circuit is connected to the input of an amplifier 119 through a differentiating circuit represented diagrammatically by the condenser 118, and the output signal is conductor 23.
- FIGURE 3 represents the signals appearing in various points of the circuits.
- the synchronization signals delivered by the local clock 102 have been shown in 3a, the time position range of 21r/3+'y in which the message signals are placed when they present themselves on the conductor 19 as shown in 3b, this in the case of FIGURES 1 and 2 in which 11:3, and a certain number of the message signals appearing in the time positions on the said conductor 19 and corresponding to a sequence of FIGURE 1 are shown in 36.
- FIGURE 3d represents the synchronization signals effectively applied to the bistable circuit 117 after being delayed in the circuit 120, this delay being symbolized by the arrow shown in dotted line linking the first pulse of FIGURE 3a to the first pulse of FIGURE 3d.
- the value of this time delay has been chosen so that the synchronization pulses are positioned in the middle of the range separating the ranges 21r/3+'y of two successive repetition periods.
- this bistable When the right part of the bistable circuit 117 is conducting, this bistable is in the 0 state and inversely.
- a signal applied to the conductive part of such a flip-flop sets it to the opposite state and the part which was conducting transmits a pulse when changing state.
- This operation is schematically symbolized on FIGURE 1, by the condenser 118.
- the state of the bistable circuit has been shown on FIGURE 36 by a low level for the 0 state and by a high level for the 1 state as shown on FIGURE 32.
- the flip-flop 117 remains in the 1 state, up to the moment when a delayed synchronization pulse appears as shown on 3a.
- This pulse applied to its 1 input resets it to the 0 state, as shown in FIGURE 3e and a pulse appears on the output conductor 22 as shown on FIGURE 3
- This pulse is free from all fluctuations since it is obtained by actuating a bistable circuit with a synchronization signal which, by definition, occupies a fixed instantaneous time position.
- the positioning of the signal on conductor 20 in the middle of the space included between two ranges of phase angle amplitude 27r/ll-l-"Y obviates all fluctuations and ambiguity in operation.
- the signal on conductor 22 is transmitted to the amplifier 119 which increases its energy content as shown on FIGURE 3g.
- the message signal definitely regenerated is thus free of any fluctuations introduced by the transmission when delivered on the output 23.
- the positioning of the synchronization signal in the middle of the space included between two ranges of amplitude 21r/n+'y may also be carried out, without the phase converter circuit 120.
- instead of controlling by a shift of the time position of the synchronization signal with respect to the rangers Zr/n-lone controls by shifting the time position of said ranges with respect to the synchronization signals.
- the normalized message signal on conductor '16 is not positioned with respect to the signal on conductor 11, so that its time position coincides with the beginning of a positive half cycle of said signal.
- the exact setting is then obtained by modifying the phase angle brought by the time delay circuit placed in the circuit 102 mentioned previously.
- the normalized message signal delivered by the circuit 101 on the conductor 16 and the synchronization signals delivered on the conductor 26 by the local clock 102 have been shown, in FIGURES 2 and 3, as ideally narrow, so that their width was small with respect to the phase angle amplitudes a. and 'y of the jitter. Obviously this has no influence at all on the operation of the discriminators 106, 107 and 108 which operate on sinusoidal signals or on that of the associated bistable circuits 109, 110, 111. However, it is necessary that the signals on conductors 19 (identical to the signals on conductor 16) and, 20 being applied to the bistable circuit 117 of circuit 103, have a duration such that the said bistable circuit may change its state in a positive way. For instance, transistor flip-flops are possible which may be activated in a positive way by signals having a duration, at half amplitude, equal to/or longer than 125 nanoseconds.
- the message signal is therefore not delayed and is in position 6". This means that, if two message signals have been received at two successive time positions in the conditions indicated here-above, the first one is delayed by 41r/ 3 and the second one is not delayed. Therefore only one regenerated pulse appears for these two input signals so that a binary number such as 11 becomes 1. A similar reasoning applies to the case where the slow fluctuation occurs in the opposite direction leads to the conclusion that this binary number 11 becomes 101.
- the error produced by the above described method is negligible because the frequency of the slow fluctuations ranges about a few cycles per hour whereas the repetition frequency of the message signals are in the range of approximately one megacycle per second.
- the circuit 101 can deliver a wide message signal on its output conductor 16.
- the discriminators and the bistable circuits associated thereto operate in the same way as in the example described formerly.
- FIGURE 4 shows the sampling circuit which can be used alternatively to the retiming circuit 103. It comprises an AND circuit 121 receiving on one of its inputs the signal appearing on conductor 19 and on the other input the signal appearing on conductor 20 suitably delayed by the circuit 122, so that it should appear in the middle of the range covered by the signals on conductor 19. During the coincidence, a pulse of same characteristics of that applied to conductor 26 appears on the output of conductor 22 and it constitutes a regenerated message signal free of fluctuations.
- a regenerative device comprising an independent local clock has been described in relation with FIGURES l, 2, 3, 4.
- the transmission of the information may be carried out on two separate lines, one reserved to the message signals, the other to the synchronization signals.
- a simplified local clock may thus be achieved and it can by well known means be brought under control of the synchronization signals which will be affected only by the slow fluctuations of the said signals, corresponding to the slow drift of a local clock.
- the jitter of these signals shall be considerably attenuated first, by applying the pulses to a narrow band filter placed at the input and second, by deriving from the signals delivered by this filter, the clock signal by means of an oscillating circuit with a surtension factor (low Q).
- a pulse code regenerative repeater for correcting incoming code pulse signals, said incoming signals having nominal frequency, means for receiving and producing normalized and reshaped signals from said incoming signals, and for generating sinusoidal signals responsive to said incoming signals, clock means for generating clock signals synchronized with said nominal frequency, a plurality of phase discriminators, each of said phase discriminators controlled jointly by the sinusoidal signals and the clock signals for generating gate control signals, n-l phase shift means for applying said clock signals to individual ones of said phase discriminators with a 21r/n phase lag relative to the preceding discriminator, wherein 21r represents the repetition period of said nominal frequency and n represents the number of phase discriminators, coincident gate means controlled by the coincidence of said gate control signals and said normalized, reshaped incoming signals for passing said normalized and reshaped signals during predetermined time periods corresponding to said nominal frequency, and means responsive to said normalized signals received from said coincident means and said clock signals for generating corrected code pulse signals and for transmitting said corrected signals.
- a pulse code regenerative repeater for correcting incoming coded pulse signals having a nominal frequency comprising means for receiving said incoming signals, means for normalizing and reshaping said incoming signals and for generating sinusoidal first control signals having the same frequency as the nominal frequency of said incoming signals, clock means for generating sinusoidal second control signals synchronized with said nominal frequency and for generating clock synchronization signals, means comprising phase discriminator means for generating register control signals responsive to the receipt of said first and second control signals with certain phase differences, means responsive to said register control signal for generating gate control signals, gate means controlled by both said gate control signals and by said normalized signals for passing said normalized signals during predetermined time periods corresponding to said nominal frequency, and means responsive to said normaiized signals and said clock synchronization signals for generating corrected coded pulses.
- said gate control signal generating means comprising means for phase shifting said second control signals a fixed fraction of a complete cycle of said nominal frequency said fraction being a function of the number of said discriminators.
- said gate control signal gen-erating means comprising register means operated under the control of said register control signals for providing gate control signals.
- said gate means including means for phase shifting the reshaped and norma ed signal received from the coincidence gate 9 1@ means so that all said received reshaped and normalized References Cited by the Examiner f ii c h iic i ii :25 $2135 if i iiy a fixed UNITED STATES PATENTS 6.
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Description
March 1966 A. E. J. CHATELON 3, ,0
PULSE REGENERATIVE DEVICES 5 Sheets-Sheet 1 Filed Oct. 11, 1961 llllllllll m 9 6 n O # 2 3 u fl m M .11 G M 8 U RU W N m H U W FOLFIIIIlnIIII l 2 2 2 2 6 M U 6 fi 9 Z mu SMM mm %H W M MOD I I 0 M H H m R a A 6 m O 8 7 N 5 a 6% M an m x 2% m 0 Dn w 0 mm M 5 D Inventor A. E. J. Clmtelon Attorney March 15, 1966 A. E. J. CHATELON 3,241,075
PULSE REGENERATIVE DEVICES 3 Sheets-Sheet 3 Filed Oct. 11, 1961 IIIL llll Ii Illllllg lllvlll AA Inventor A. E. J. Chatelon w Allorne y United States Patent Oil ice 3,24Lfi75 Patented Mar. 15, 1966 3,241,075 PULSE REGENERATIVE DEVICES Stoppard Joseph Chatelon, Montrouge, Seine, France, assignor to international Standard Electric Corporation, New York, N.Y., a corporation of Delaware Filed Get. 11, 1961, Ser. No. 144,354 Jiaims priority, application France, Get. 17, 1966, 841,358, Patent 1,277,331 6 Claims. (Ci. 328-169) The present invention concerns improvements in the operation of regenerative devices inserted in telecommunication systems transmitting pulse type data.
It concerns more particularly the suppression of the errors due to small amplitude jitter superimposed on slow fluctuations of the time positions of pulses belonging to a group of code signals.
In the information transmission process called Pulse Code Modulation or PCM," the digitalized informations are expressed in a binary code wherein the digits characterizing the different weights are transmitted sequentially in order to occupy regularly space time slots.
In such a code, each digit time slot contains one of the two figures: 1 characterized by the presence of a pulse or characterized by the absence of a pulse.
This modulation system may be used for the transmission of voice frequency signals or telegraph signals and more generally for data transmission. It is well known that in such an operation the time positions of the pulses (called message signals) may be affected by certain fluctuations.
Thus, the variations of the propagation conditions in the medium used to carry out the transmission (telephone pair, coaxial cable or waveguide, radio link, etc.) introduce a variation of the repetition frequency of the message signals. These variations are called slow fluctuations and have a repetition frequency of about a few cycles per hour and a time period amplitude equal to a number of digit time slots.
On the other hand, the crosstalk between the different transmission ways, noise in the propagation medium, induction effects due to industrial frequency alternating voltages, etc., introduce fast fluctuations or jitter on either side of the mean position of the message signals. The mean position of the message signals is where they would be found if they were affected only by slow fiuctuations. The repetition frequency of the fast fluctuations whose amplitude is relatively small may vary from a few cycles up to several tens of kilocycles per second. The jitter also interferes during the reshaping of the message signals in the regenerative device.
On the other hand, in order to accurately define the time positions of the signals delivered by the regenerative device, it is necessary to include therein a circuit delivering synchronization signals at the time at which the message signals are aligned.
When the synchronization signals are obtained from pulses at the transmission point, they are aiiected by the same slow fluctuations that affect the message signal pulses themselves. When they are obtained from an independent clock placed in the repeater their frequency cannot remain identical to that of synchronization pulses obtained during transmission even though they are also affected by a slow drift.
In the regenerative devices according to the previous art, a new signal free of fluctuations is obtained. by comparing, in a coincidence circuit, a signal derived from the message signal to a signal delivered by the local clock. In one of these devices, a reshaped message signal is compared to a gate signal of a relatively long duration but shorter than the time interval separating the theoretical positions of two signals in adjacent digit time slots. If the message signal is inside the gate signal, the coincidence circuit delivers a signal which is afterwards placed in a well determined time position.
In this operation, a message signal may be lost either when it is placed in such a position that the gate signal does not exist, or when it coincides with one of the edges of the said signal, in which case an uncertainty exists in that the coincidence circuit may not operate if the overlapping of the two signals is not sufficient. When the message signal is affected by jitter, the coincidence may take place on a time position adjacent to the exact time position to which the said signal belongs.
The object of the present invention is therefore to suppress, in the regenerative devices, the errors due to low amplitude jitter superimposed on slow fluctuations of whatsoever amplitude which affects the time positions of pulses belonging to a group of code signals.
The invention will be particularly described with reference to the accompanying drawings in which:
FIGURE 1 shows a block diagram of an exemplary circuit made according to the invention;
FIGURE 2 shows the phase relation between the signals set into action in the circuit;
FIGURE 3 shows the signal appearing in several points of the circuit;
FIGURE 4 shows a sampling circuit used as an alternative circuit.
FIGURE 1 is a diagrammatic representation of a means for achieving the desired results according to the invention. The message signal is received at the input of the regenerative device on conductor 10 and is applied to the circuit 101 for extraction of the input reference. This circuit comprises first a pulse shaping device of any well known type, delivering on output conductor 16 normalized pulses and second a circuit which delivers a sinusoidal reference signal having the same frequency as the repetition frequency of the pulses received on the conductor 10. For example, this circuit may comprise a bandpass filter tuned to the nominal repetition frequency of the pulses received which, when energized by the normalized signals, delivers a sinusoidal signal on output conductor 11 of the circuit 101. Since this filter presents a relatively high surtension factor (high Q), a message signal gives rise toa certain number of cycles and the delivered signal may be considered as being permanent. This sinusoidal signal presents a constant phase relation with respect to the average position of the message signal so that it follows the slow fluctuation and it defines the time scale on which the received message signals are positioned.
This sinusoidal signal is also affected by a certain amount of jitter. The jitter of the message signals and the jitter caused by the filter itself affects the sinusoidal signal. It has been found that the time period of this jitter is at most equal to a While the time period of the jitter of the message signal is equal at most to 1 both shown in FIG. 2. The normalized message signal delivered by the circuit 101 has a Width clearly lower than or and 'y. A local clock 102 is tuned to the nominal frequency of the synchronization signal used at the transmission and delivers a sinusoidal signal of same frequency on its output conductor 12 which is applied to one of the 3 inputs of the three phase discriminators 196, 1G7, 163 after the phase of the signal has been shifted respectively by 0, 21/3 and 41r/3 by the phase shifters 194 and 105'. The second input of each one of the discriminators receives the sinusoidal signal at the repetition frequency of the message signal transmitted over the conductor 11.
Each discriminator delivers a signal only when the phase angle between the two signals applied to it does not exceed 21r/30t, so that the time period of its range of operation is 2TF/3Ot. The output of each one of the discriminators 1%, 1117 and 108 is connected respectively to the input referenced O of the bistable circuits or flipfiops 109, 1111 and 111. These circuits are connected together in a way such that the setting of one of them from the state to the 1 state, resets the two others in the 0 state. The output conductors 13, 14 and 15 referenced 1, of each one of the bistable circuits are respectively connected to one of the inputs of the AND circuits 112, 113, 114.
The second input 16 of each one of these AND circuits receives from the circuit 101, the normalized message signals. The output conductors 17, 18, 19 of these AND circuits are connected to the retiming circuit 103, after passage, for the signals delivered by the AND circuits 113 and 112, through the delay circuits 115 and 116 which provide respectively delays corresponding to phase angles of 21r/ 3 and 41r/ 3. The retiming circuit 103 receives on its input conductor synchronization pulses delivered by the local clock 1(22.
Each of the conductors 19 and 26 is connected to one input of a bistable flip-flop circuit 117. The signal appearing on conductor 19 sets the flip-flop in the 1 state, then, the signal appearing on conductor 20 resets it to the 0 state and delivers a pulse on the conductor 22, the time position of which is that of the synchronization signal 20. The signal is amplified in the circuit 119 and appears on output conductors 23.
The phase relations between the involved signals of the circuit shall be described now based on FIG. 2.
FIGURE 2a shows the duration of a repetition period of the synchronization signal delivered by the local clock 102 on the conductor 12 subdivided in to radians and degrees. a
In the course of the description, the operational ranges of the discriminators and the phase angles between the different signals will be characterized by their angular value by taking for the positive phase direction, the direction OX corresponding to a time lag.
It has been seen during the study of FIGURE 1, that a comparison was made in the discriminators of a signal delivered by a local clock and a signal using a time scale on which are positioned the received message signals. Since the local clock and the clock located in the place from which the message signals are transmitted both have a very high frequency stability ranging about 10- per example, and since the slow fluctuations brought about by the transmission medium are very low in frequency, the frequency difference between the signals compared is also very low and presents itself as a variable phase displacement with respect to the time. This variation has an extremely low rate, and the phase angle may be considered in fact as constant during several repetition periods. During the following description of the operation, it will be assumed that the frequency of the local clock is ideally stable, since its slow drift may be considered as similar in nature to the slow fluctuation of the message signal.
In these conditions, the discriminator 106 which receives the signals present on conductors 11 and 12 delivers a signal when the phase angle between these two signals ranges between 0 and 27r/3oc. it is thus possible to draw, FIGURE 2b, the line segment of AB of length equal to 21r/3oc which represents the range of operation of the discriminator. The origin of which, A, is aligned with the beginning of the repetition period of signal 12 marked 0 (zero) on the FIGURE 2a.
The signal delivered by this discriminator 106 is applied to the bistable circuit 1199 which sets to the 1 state, resetting at the same time the bistable circuits 119 and 111 which were in the 1 state. A signal appears on the output 13 of the bistable circuit 169 which activates the AND circuit 112. When the phase angle between the signals on conductors 11 and 12 is in the range between 21r/3-rx and 2rr/3, the discriminator 1116 does not deliver any signal and the bistable circuit 1&9 which remains in the 1 state still activates the AND circuit 112. When this phase angle ranges between 21r/ 3 and 41r/3-0t the discriminator 1117 delivers a signal in its operation range A'B' which sets the fiip-fiop 1111 to the 1 state; consequently, the AND circuit 113 is activated. When the phase angle ranges between 41r/3 and 2rrcc the AND circuit 114 is activated by the bistable circuit 111. It is seen therefore that the ranges of operation, AB, AB', A"B" of the three discriminators are separated by ranges of non operation A A, BA and BA of amplitude at the purpose of which is to prevent the jitter of the signal 11 from disturbing the bistables associated with it.
If for example, the phase angle between the signals on conductors 11 and 12 are higher than 21r/3u, then the operation of the circuit takes place within the range BA, and the signal on conductor 11 is affected by a jitter of amplitude tit/2 on either side of its mean position. It is seen that whatever he the position of the signal in the range it can activate only one of the discriminators 1% or 107. Therefore with this exemplary circuit there could not be any cornmutations between the two adjacent bistable circuits 109 and due to the jitter of the sinusoidal signal on conductor 11. In short only one of the AND circuits 112, 113, 114 is activated for a given phase angle between the sinusoidal signals on conductors 11 and 12.
The way according to which the normalized signal delivered on the conductor 16 by the circuit 1111 is treated by the circuit just described will be disclosed immediately hereafter.
The signal on conductor 16 is positioned with respect to the corresponding signal on conductor 11 so that its time position coincides with the beginning of a positive haif cycle of said signal on conductor 11, this being accomplished easily with a time delay circuit placed in the circuit 1111. FIGURE 20 shows a certain number of these normalized signals, 1, 2, 3, 4, 5 and 6 which occupy various time positions which will be always referenced With respect to the time scale of FIGURE 2a.
The signal 1 of the FIGURE 20 occupies a time position equal to the time position of the associated signal on conductor 11 and therefore presents a phase angle less than 21r/3ot with respect to the signal on conductor 12. The discriminator 106 delivers, therefore, a signal to the flip-flop 109 which activates the input conductor 13 of the AND circuit 112. The message signal is applied on the second input conductor 16 of this AND circuit which thus delivers on its output conductor 17 and identical signal at the same time position 1. This signal undergoes a phase shift of 411'/ 3 in the circuit 116 before being applied to the input conductor 19 of the retiming circuit 103.
FIGURE 2d shows in 1', the time position of this delayed signal. If this signal is affected by a jitter of maximum amplitude 'y, as shown hachured on FIGURE 20, this jitter is found once again on the conductor 19 on either side of the time position 1'.
Also, if the message signal occupies the time position 2 because of a slow fluctuation in a positive direction, the discriminator 1126 delivers a signal. This signal 2 is thus found again, on the conductor 19, in the time position 2. If this signal is afiected by the jitter shown hachured, and if the signal 11 associated with it is placed at certain instants in the nonoperational range of the discriminators, nevertheless the bistable unit 109 keeps control and activates the AND circuit 112.
When the message signal occupies the position 3, the AND circuit 113 is activated and the signal which it delivers is out of phase by 21r/3 in the circuit 115. Therefore, on the conductor 19 the signal is in position 3'. The same procedure applies to the signal in position 4 which is transferred to position 4'.
If the signal is in the position 5, it is transmitted Without any dephasing over conductor 19 and is placed in position 5'.
If the signal formerly placed in position 1 and the sinusoidal signal derived therefrom are jointly attected by a slow fluctuation, first in a positive phase direction then in the negative phase direction, the associated bistable circuit keeps the control of the AND circuit to which it is connected over a maximum phase angle of 21r/3+or of slow fluctuations.
More generally, if the circuit according to the invention comprises a fixed number, such as n, discriminators the control range of each one of the associated flip-flops is a phase angle of 21r/n+ut.
In the case of the example just studied, a message signal whose associated sinusoidal signal is placed between the points on and 21r/ 3 is displaced by 41r/3 before being applied to the input 19 of the retiming circuit 1133. Its time position is thus placed, on this input 19, in a maximum range extending from i.e., in the range 47r/3Ot to 211'.
A message signal whose associated sinusoidal signal is placed between the point 21r/ 3-nt and 41r/ 3 is displaced by 21r/3 and is also placed in the range 41r/30c to 21r. The time position of a message signal whose associated sinusoidal signal is placed between the points 41r/3a and Zn is not modified.
The range occupied by the shifted message signals of the FIGURE 2d shall now be determined. Let us consider for instance the signal 9, FIGURE 26, whose associated sinusoidal signal is placed in the middle of the nonoperation range BA. If this position has been reached because of a slow fluctuation in the negative direction, it is the discriminator 167 which delivers a signal. In these conditions the signal 9 is carried back in 9', FIGURE 2d. If this position has been reached because of a slow fluctuation in the positive direction, it is the discriminator 106 which delivers a signal. The signal 9 is then placed in 9", FIGURE 2d. The jitter of these signals is shown hachured, and it is seen that, whatever the mean time position of a signal afiected by jitter and by slow fluctuations may be, the device, according to the invention, places it inside a range extending between 41r/3'y and Zr, it z; or inside a range extending between 41r/3-a and Zr, if Y OL In the course of the description, it will be assumed as a nonlimitative example that 'y ct.
The retiming circuit 103 receives on its input conductor 20 signals delivered by the local clock 162 and on its input conductor 19 the message signals which, as seen previously, are placed inside time position ranges of duration 21r/it-I-7 such as shown on 7a and 7b, FIGURE 2e, and are still affected by their jitter.
It has been seen during the study of FIGURE 1, that these signals are respectively applied to the inputs of a bistable circuit 117, the signal on conductor 19 being applied to the input 0 and the signal on conductor 20 to the input 1. The 1 output of this bistable circuit is connected to the input of an amplifier 119 through a differentiating circuit represented diagrammatically by the condenser 118, and the output signal is conductor 23.
The operation of this circuit 103 will be explained now in relation with FIGURE 3 which represents the signals appearing in various points of the circuits.
The synchronization signals delivered by the local clock 102, have been shown in 3a, the time position range of 21r/3+'y in which the message signals are placed when they present themselves on the conductor 19 as shown in 3b, this in the case of FIGURES 1 and 2 in which 11:3, and a certain number of the message signals appearing in the time positions on the said conductor 19 and corresponding to a sequence of FIGURE 1 are shown in 36.
FIGURE 3d represents the synchronization signals effectively applied to the bistable circuit 117 after being delayed in the circuit 120, this delay being symbolized by the arrow shown in dotted line linking the first pulse of FIGURE 3a to the first pulse of FIGURE 3d. The value of this time delay has been chosen so that the synchronization pulses are positioned in the middle of the range separating the ranges 21r/3+'y of two successive repetition periods.
When the right part of the bistable circuit 117 is conducting, this bistable is in the 0 state and inversely.
Besides, a signal applied to the conductive part of such a flip-flop sets it to the opposite state and the part which was conducting transmits a pulse when changing state. This operation is schematically symbolized on FIGURE 1, by the condenser 118. The state of the bistable circuit has been shown on FIGURE 36 by a low level for the 0 state and by a high level for the 1 state as shown on FIGURE 32.
The flip-flop 117 remains in the 1 state, up to the moment when a delayed synchronization pulse appears as shown on 3a. This pulse applied to its 1 input, resets it to the 0 state, as shown in FIGURE 3e and a pulse appears on the output conductor 22 as shown on FIGURE 3 This pulse is free from all fluctuations since it is obtained by actuating a bistable circuit with a synchronization signal which, by definition, occupies a fixed instantaneous time position. The positioning of the signal on conductor 20 in the middle of the space included between two ranges of phase angle amplitude 27r/ll-l-"Y obviates all fluctuations and ambiguity in operation.
The signal on conductor 22 is transmitted to the amplifier 119 which increases its energy content as shown on FIGURE 3g. The message signal definitely regenerated is thus free of any fluctuations introduced by the transmission when delivered on the output 23.
The positioning of the synchronization signal in the middle of the space included between two ranges of amplitude 21r/n+'y may also be carried out, without the phase converter circuit 120. In this case, instead of controlling by a shift of the time position of the synchronization signal with respect to the rangers Zr/n-lone controls by shifting the time position of said ranges with respect to the synchronization signals. The normalized message signal on conductor '16 is not positioned with respect to the signal on conductor 11, so that its time position coincides with the beginning of a positive half cycle of said signal. The exact setting is then obtained by modifying the phase angle brought by the time delay circuit placed in the circuit 102 mentioned previously.
The normalized message signal delivered by the circuit 101 on the conductor 16 and the synchronization signals delivered on the conductor 26 by the local clock 102 have been shown, in FIGURES 2 and 3, as ideally narrow, so that their width was small with respect to the phase angle amplitudes a. and 'y of the jitter. Obviously this has no influence at all on the operation of the discriminators 106, 107 and 108 which operate on sinusoidal signals or on that of the associated bistable circuits 109, 110, 111. However, it is necessary that the signals on conductors 19 (identical to the signals on conductor 16) and, 20 being applied to the bistable circuit 117 of circuit 103, have a duration such that the said bistable circuit may change its state in a positive way. For instance, transistor flip-flops are possible which may be activated in a positive way by signals having a duration, at half amplitude, equal to/or longer than 125 nanoseconds.
When a message signal is in the time position 6, FIG- URE 2c, the theoretical position of the origin of the sinusoidal signal coincides with the middle of the segment A A. If this position has been reached because of a slow fluctuation in the phase negative direct-ion (phase lead), it is known that the message signal is out of phase by 41r/ 3 on the conductor 19, in 6' FIGURE 2d. If the message signal position moves by a few degrees in the negative direction, the position of the associated sinusoidal signal moves, as a first approximation, by the same amount. If said signal is affected by its maximum jitter, it my pass over point A in the negative direction, and activate the discriminator 108 which would happen anyway if the slow fluctuation continued in the same direction. The message signal is therefore not delayed and is in position 6". This means that, if two message signals have been received at two successive time positions in the conditions indicated here-above, the first one is delayed by 41r/ 3 and the second one is not delayed. Therefore only one regenerated pulse appears for these two input signals so that a binary number such as 11 becomes 1. A similar reasoning applies to the case where the slow fluctuation occurs in the opposite direction leads to the conclusion that this binary number 11 becomes 101.
The error produced by the above described method is negligible because the frequency of the slow fluctuations ranges about a few cycles per hour whereas the repetition frequency of the message signals are in the range of approximately one megacycle per second.
'In another exemplary device utilizing the invention, the circuit 101 can deliver a wide message signal on its output conductor 16. The discriminators and the bistable circuits associated thereto operate in the same way as in the example described formerly.
If M is the total width occupied by one of these wide message signals plus the jitter by which it is affected, the signals on the conductor 19 occupy a range of Since such a wide signal must be narrower than one repetition period, than 21r/n|-w+oc Z1r. Therefore the condition: w 21r/ (fZl)It-oz prevails.
FIGURE 4 shows the sampling circuit which can be used alternatively to the retiming circuit 103. It comprises an AND circuit 121 receiving on one of its inputs the signal appearing on conductor 19 and on the other input the signal appearing on conductor 20 suitably delayed by the circuit 122, so that it should appear in the middle of the range covered by the signals on conductor 19. During the coincidence, a pulse of same characteristics of that applied to conductor 26 appears on the output of conductor 22 and it constitutes a regenerated message signal free of fluctuations.
A regenerative device comprising an independent local clock has been described in relation with FIGURES l, 2, 3, 4. In some cases the transmission of the information may be carried out on two separate lines, one reserved to the message signals, the other to the synchronization signals. A simplified local clock may thus be achieved and it can by well known means be brought under control of the synchronization signals which will be affected only by the slow fluctuations of the said signals, corresponding to the slow drift of a local clock. Since the information received on the synchronization line is made up of a sequence of uninterrupted pulses, the jitter of these signals shall be considerably attenuated first, by applying the pulses to a narrow band filter placed at the input and second, by deriving from the signals delivered by this filter, the clock signal by means of an oscillating circuit with a surtension factor (low Q).
In the study of FIGURE 2, the operation of the circuit according to the invention is shown in 2's, in presence of a,
slow fluctuation of the message signal, by setting the discrimination ranges of FIGURE 2b to occupy fixed time positions. It is evident that even if there is a slow drift of the local clock signal producing a shift in the time positions of the whole of the discrimination ranges, the resulting effect is exactly the same as that produced by the slow fluctuation of the message signals. The device according to the invention this compensates also for the slow drift effect of the local clock whether the latter is autonomous or synchronized by signals transmitted for this purpose over a separate line.
While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly undersood that this description is made only by way of example and not as a limitation on the scope of the invention.
I claim:
1. In a pulse code regenerative repeater for correcting incoming code pulse signals, said incoming signals having nominal frequency, means for receiving and producing normalized and reshaped signals from said incoming signals, and for generating sinusoidal signals responsive to said incoming signals, clock means for generating clock signals synchronized with said nominal frequency, a plurality of phase discriminators, each of said phase discriminators controlled jointly by the sinusoidal signals and the clock signals for generating gate control signals, n-l phase shift means for applying said clock signals to individual ones of said phase discriminators with a 21r/n phase lag relative to the preceding discriminator, wherein 21r represents the repetition period of said nominal frequency and n represents the number of phase discriminators, coincident gate means controlled by the coincidence of said gate control signals and said normalized, reshaped incoming signals for passing said normalized and reshaped signals during predetermined time periods corresponding to said nominal frequency, and means responsive to said normalized signals received from said coincident means and said clock signals for generating corrected code pulse signals and for transmitting said corrected signals.
2. A pulse code regenerative repeater for correcting incoming coded pulse signals having a nominal frequency comprising means for receiving said incoming signals, means for normalizing and reshaping said incoming signals and for generating sinusoidal first control signals having the same frequency as the nominal frequency of said incoming signals, clock means for generating sinusoidal second control signals synchronized with said nominal frequency and for generating clock synchronization signals, means comprising phase discriminator means for generating register control signals responsive to the receipt of said first and second control signals with certain phase differences, means responsive to said register control signal for generating gate control signals, gate means controlled by both said gate control signals and by said normalized signals for passing said normalized signals during predetermined time periods corresponding to said nominal frequency, and means responsive to said normaiized signals and said clock synchronization signals for generating corrected coded pulses.
3. In a phase regenerative repeater according to claim 2, said gate control signal generating means comprising means for phase shifting said second control signals a fixed fraction of a complete cycle of said nominal frequency said fraction being a function of the number of said discriminators.
In a phase regenerative repeater according to claim 2, said gate control signal gen-erating means comprising register means operated under the control of said register control signals for providing gate control signals.
5. In the regenerative repeater of claim 1, said gate means including means for phase shifting the reshaped and norma ed signal received from the coincidence gate 9 1@ means so that all said received reshaped and normalized References Cited by the Examiner f ii c h iic i ii :25 $2135 if i iiy a fixed UNITED STATES PATENTS 6. In the regenerative repeater of claim 5, including 2,669,706 2/1954 Gray 328410 a retiming means operated under the control of said clock 5 27861O0 2/1957 Earp 328-141 signals and said reshaped and normalized phase shifted 2866092 19 58 Raynsford 328109 signals received through said gate means for generating jitter free coded pulse signals that occur during :said pre- ARTHUR GAUSS Pnmmy Examine" determined time periods. JOHN W. HUCKERT, Examiner.
Claims (1)
1. IN A PULSE CODE REGENERATIVE REPEATER FOR CORRECTING INCOMING CODE PULSE SIGNALS, SAID INCOMING SIGNALS HAVING NOMINAL FREQUENCY, MEANS FOR RECEIVING AND PRODUCING NORMALIZED AND RESHAPED SIGNALS FROM SAID INCOMING SIGNALS, AND FOR GENERATING SINUSOIDAL SIGNALS RESPONSIVE TO SAID INCOMING SIGNALS, CLOCK MEANS FOR GENERATING CLOCK SIGNALS SYNCHRONIZED WITH SAID NOMINAL FREQUENCY, A PLURALITY OF PHASE DISCRIMINATORS, EACH OF SAID PHASE DISCRIMINATORS CONTROLLED JOINTLY BY THE SINUSOIDAL SIGNALS AND THE CLOCK SIGNALS FOR GENERATING GATE CONTROL SIGNALS, N-1 PHASE SHIFT MEANS FOR APPLYING SAID CLOCK SIGNALS TO INDIVIDUAL ONES OF SAID PHASE DISCRIMINATORS WITH A 2$/N PHASE LAG RELATIVE TO THE PRECEDING DISCRIMINATOR, WHEREIN 2$ REPRESENTS THE REPETITION PERIOD OF SAID NOMINAL FREQUENCY AND N REPRESENTS THE NUMBER OF PHASE DISCRIMINATORS, COINCIDENT GATE MEANS CONTROLLED BY THE COINCIDENCE OF SAID GATE CONTROL SIGNALS AND SAID NORMALIZED, RESHAPED INCOMING SIGNALS FOR PASSING SAID NORMALIZED AND RESHAPED SIGNALS DURING PREDETERMINED TIME PERIODS CORRESPONDING TO SAID NOMINAL FREQUENCY, AND MEANS RESPONSIVE TO SAID NORMALIZED SIGNALS RECEIVED FROM SAID COINCIDENT MEANS AND SAID CLOCK SIGNALS FOR GENERATING CORRECTED CODE PULSE SIGNALS AND FOR TRANSMITTING SAID CORRECTED SIGNALS.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR841358A FR1277331A (en) | 1960-10-17 | 1960-10-17 | Improvements to pulse regeneration devices |
Publications (1)
Publication Number | Publication Date |
---|---|
US3241075A true US3241075A (en) | 1966-03-15 |
Family
ID=8740907
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US144354A Expired - Lifetime US3241075A (en) | 1960-10-17 | 1961-10-11 | Pulse regenerative devices |
Country Status (3)
Country | Link |
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US (1) | US3241075A (en) |
BE (1) | BE609233A (en) |
FR (1) | FR1277331A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0004887A1 (en) * | 1978-04-04 | 1979-10-31 | CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. | Method and device for synchronizing digital transmissions via satellite |
EP0140042A2 (en) * | 1983-09-20 | 1985-05-08 | Nec Corporation | Digital phase lock loop circuit |
EP0157701A2 (en) * | 1984-03-29 | 1985-10-09 | Fujitsu Limited | Phase synchronization circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2669706A (en) * | 1950-05-09 | 1954-02-16 | Bell Telephone Labor Inc | Code selector |
US2786100A (en) * | 1950-12-01 | 1957-03-19 | Int Standard Electric Corp | Pulse communication systems |
US2866092A (en) * | 1954-04-27 | 1958-12-23 | Vitro Corp Of America | Information processing device |
-
1960
- 1960-10-17 FR FR841358A patent/FR1277331A/en not_active Expired
-
1961
- 1961-10-11 US US144354A patent/US3241075A/en not_active Expired - Lifetime
- 1961-10-17 BE BE609233A patent/BE609233A/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2669706A (en) * | 1950-05-09 | 1954-02-16 | Bell Telephone Labor Inc | Code selector |
US2786100A (en) * | 1950-12-01 | 1957-03-19 | Int Standard Electric Corp | Pulse communication systems |
US2866092A (en) * | 1954-04-27 | 1958-12-23 | Vitro Corp Of America | Information processing device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0004887A1 (en) * | 1978-04-04 | 1979-10-31 | CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. | Method and device for synchronizing digital transmissions via satellite |
EP0140042A2 (en) * | 1983-09-20 | 1985-05-08 | Nec Corporation | Digital phase lock loop circuit |
EP0140042A3 (en) * | 1983-09-20 | 1986-08-27 | Nec Corporation | Digital phase lock loop circuit |
EP0157701A2 (en) * | 1984-03-29 | 1985-10-09 | Fujitsu Limited | Phase synchronization circuit |
EP0157701A3 (en) * | 1984-03-29 | 1987-09-09 | Fujitsu Limited | Phase synchronization circuit |
US4713621A (en) * | 1984-03-29 | 1987-12-15 | Fujitsu Limited | Phase synchronization circuit |
Also Published As
Publication number | Publication date |
---|---|
BE609233A (en) | 1962-04-17 |
FR1277331A (en) | 1961-12-01 |
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