SU1429321A1 - Delta-coder - Google Patents

Abstract

The invention relates to automation and communication technology. Its use in information transmission systems using delta modulation allows to increase the reliability of operation of the delta coder, which contains a comparator 1, trigger 2, shift register 3, elements 4-7, elements IL, 9, 9, reversible counter 10, code converter 11, digital integrator 12, decoders 13, 14, and NOT elements 15, 16. By introducing a frequency divider 17, delay element 18, and shift register 19, the delta coder is simplified, and there is no need for an extra synchronization channel when transfer. 2 Il.

Description

The invention relates to automation and communication technology and can be used in information transmission systems using delta modulation.

The purpose of the invention is to increase the reliability of operation.

FIG. 1 is a functional diagram of the delta coder5 of FIG. 2 - time diagrams of the signals at the input And the outputs of the delay element, I Delta coder contains a comparator 1 | J trigger 2j first register 3 shifts Ga, first-quarter elements AND 4-7 first 8 and second 9 elements OR, reversible counter 10, code converter |) user 11, digital integrator 12, first 13 to second 14 decoder- |) Ы , the first 15 and second, 16 elements are NOT, the frequency divider 17, the element is 18 and the second shift register 19, kpoMe, the delta coder has an informational 20 and clock 21 inputs and output 22 ..

The code converter 11 is made, on the fixed memory unit and the block; Multiplexers, connecting to the outputs of the code converter 11, the corresponding outputs of the fixed memory unit according to the signals on its control inputs.

Digital integrator 12 is made on an arithmetic logic unit, a digital-analog converter and a buffer register, the outputs of which are connected to the inputs of the digital-analog converter and the first inputs of the arithmetic logic unit, the outputs of which are connected to the information inputs of the buffer register, whose control input The clock input of the digital integrator 12, the second information and control inputs of the arithmetic logic unit and the output of the digital-to-analog converter, respectively, the information vhodag landmark and-hsi vykodo s digital integrator 12,

. The first 13 and second 14 decoders are used to indicate that the reversible counter 10 reaches the maximum and minimum values (quantization step), respectively.

Element 18 delay on the clock pulses at the input (Fig „2a) forms on the first and second outputs a delay, a sequence of pulses (Fig. 26 and b), Perv and the second outputs of the second shift register 19

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are outputs of its first and last bits.

The first shift register 3, AND 4 and 5, and OR 8 is a digital delta modulated (TO) signal analyzer.

The delta encoder works as follows.

The digital DM signal, formed as a result of comparing the input U (O and approximate U (t) signals by the comparator 1 and comparing the results of the comparison with trigger 2, sequentially fills the bits of the shift register 3 and analyzes the elements 4 and 5 of IL 8. The results of the analysis in the form of a digital signal are recorded in the shift register 19 and are advanced 3 times with the arrival of the clock w-outputs from input 21. In each clock cycle the information recorded in the shift register is through the third 7. and a quarter of the elements and the second element OR 9 affect the counting inputs re Versatile counter 10 "In addition to Toroj, the third inputs of the And 7 and 8 elements receive signals from the first and second outputs of the delay element 13, - the input of which is post-nasQT clock pulses. The signal at the first output of the delay element 18 is delayed (shifted) relative to the input signal for some arbitrary time, and the signal at the second output of the delay element 18; d for the time cTj, J and C sf but l T, where Tj) is the period of the clock frequency.

Thus, in each clock cycle, the third inputs of the And 7 and 8 elements alternately (with an interval of b. G) affect the scanning pulses, first switching the information bit from the first bit of the shift register 19 to the forward count input of the reversible counter 10, and then - the shift bit from the last bit of the shift register 19 to the input of the reverse counting of the reversible counter 20. The state of the reversing counter 10 thus constantly reflects the density (ratio of single and r /., pegs of packs) of a 7-digit DM signal on some fragment ( inter ale), the duration of which is determined by a width of shift register 6. The duration of the analyzed fragment should be chosen within the range of 3–10 ms, which, at clock frequencies of 16–32 kHz, allows one to choose a bit.

the stability of the J9 shift register is in the range of 50–300, depending on the specific clock frequency and the required inertia of adaptation. The code combination at the outputs of the reversible counter 10 is further used to form a specific quantization step (a binary number representing the quantization step) at the output of the code converter 11. The approximation signal is restored using a digital integrator.

The decoders 13 and 14, in combination with the first 15 and second 16 elements, do NOT create the locking circuit of the extreme states of the reversible counter 10 in idle mode and momentary overload of the encoder to eliminate failures associated with the overload of the reversible counter 10.

The frequency divider 17 and the second element OR 9 are used to clean the reversible counter 10 from the results of the effects of noise and faults in the digital D-signal. The division factor of the 17 divider frequency is advisable to be chosen so that the pulses, starting from time to time to the input of the counting counter of the reversible counter 10 (and decreasing the binary number at its outputs), do not have a decisive influence on the quantization step during the transmission of the useful signal , but whether the meter 10 is allowed to be freed from the results of joys (and not to accumulate them during the whole operation time). In practice, the division factor is recommended to choose within 10-20, which specifically depends on the noise of the communication channel.

Thus, due to the method of controlling the quantization step size in the companding circuit in the delta coder without an additional sync channel, the adjustment (adaptation) of the quantization step required for the transmitted signal parameters is required. There is no need for an additional synchronization channel, which leads to an increase in operational stability due to the absence of a fundamental possibility of synchronization failures, reduction of synchronization equipment and minimization of the time taken to synchronize on the receiving side.

The proposed delta coder (and, in particular, its adaptation chain) has

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A simpler implementation than the well-known one, which, in turn, also provides for better stability and reliability.

Claims (1)

Invention Formula The delta coder containing the comparator, the first input of which is the information input of the delta coder, the output of the comparator is connected to the information input of the trigger, the output of which is connected to the information input of the first shift register, the sign input of the digital integrator, and is the output of the second coder, direct and the inverse outputs of the bits of the first shift register are connected to the inputs of the first and atomic elements AND, respectively, - the codes of which are connected to the inputs of the first element OR, the second element OR, the reversible counter, the outputs of which are connected to the inputs of the code converter, the outputs of which are connected to the information ABOUT The inputs of the digital integrator, the output of which is connected to the second input of the comparator, are the first and second decoders, the outputs of which are connected through the elements of the same name NOT to the first inputs of the third and fourth elements AND, the output of the third element AND, respectively, of the reversible counter, the trigger inputs of the trigger, the first p; the shift horn and the digital integrator are combined and are a clock input of the delta coder, different Teivi, which, in order to increase the reliability of the fowling function, in the delta coder enter Here, the second shift register, the delay element and the frequency divider, whose input is combined with the input of the delay element and the clock input of the second shift register and connected to the clock input of the delta encoder, the output of the first OR element is connected to the information input of the second shift register, whose first and second outputs connected to the second inputs of the third and fourth elements, respectively; the first and second outputs of the delay element are connected to the third inputs of the third and fourth elements, respectively; the outputs of the divider are often s and fourth AND gates are connected to first and second inputs of the second OR gate whose output is connected 514293216 with the reverse countdown input with the inputs of the first and second decoder counter, the outputs of which are connected to the rator. but 1G 9 games 2