SU1115069A1 - Function generator - Google Patents

Abstract

The FUNCTIONAL CONVERTER containing the input register, connected by information inputs to the argument input bus, the low-order bits, the low-order bits of the first group of inputs of the first block of code subtraction, and the high-bit outputs of the decoder connected to the address inputs of the block the memory connected by the outputs with the first group of inputs of the second block of code subtraction connected by the outputs of the lower bits of the difference code to the installation inputs of the controlled frequency divider and the output cleared - to the control input of setting the code of the controlled frequency divider and to the first input of the OR element connected by the output to the first input of the AND element connected by the second input to the output of the pulse generator, and the output to the signal input of the controlled frequency divider whose output is connected to counting input of the first reversible counter, and the first buffer register, characterized in that, in order to catch the speed of the functional converter, a sawtooth voltage generator, multiplying the digital tax converter, second buffer register, modulo-two adder, second reversible counter, analog-to-digital converter, sign register, digital-to-analog converter and output summing amplifier connected by the first input to the output of the digital-to-analog converter, and the second input to the output of the multiplying digital-analog converter and input an analog-to-digital converter connected by outputs to the inputs of the higher bits of the second buffer register connected by inputs of the lower bits to the gates I give the first reversible counter, and the codes to the second group of inputs of the second block of code subtraction and to the digital inputs of the digital-to-analog converter connected to the gate input, to the output of the OR element and to the input of the sawtooth generator which is connected to the output of the modulo two adder and to the control input of the reverse of the first reversible counter, and the output to the analog input of the multiplied digital-to-analog converter connected by digital inputs from the output The code of the difference of the second block of the code subtraction, and the control input of the Stop code with the gate input of the decoder, the input of the recording control of the first buffer register and the zero output of the second block of the code subtraction, connected by the output of the sign of the difference

Description

to the first input of the modulo two adder, connected by the second input to the CASE of the character register code connected by the record control input to the second input of the OR element, the record control input of the input register and the zeroing output of the first block of the code subtraction, the higher bits of the first group of inputs of which are connected to. the outputs of the higher bits of the input register and the information inputs of the first

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the buffer register, the upper bits of the second group of inputs are with the outputs of the first buffer register, and the lower bits of the second group of inputs are with the outputs of the second reversible counter connected by a counting input to the output of the AND element, and the control input of the reverse are to the output of the difference sign of the first block code reading and register information input

i sign.

The invention relates to automation and computing, in particular, to piecewise linear approximation devices, and can be used in hybrid computing systems and complexes with a functional digital-to-analog converter.

A functional converter is known, comprising a pulse generator, counters, a code comparison unit, registers, a code-frequency converter, a memory block, a decoder, a reversible counter, and an output digital-to-analog converter SP.

The disadvantage of a functional converter is a slower response.

The closest to the invention is a functional converter containing an input register connected by information inputs to the argument input bus, the low-order outputs to the lower bits of the first group of inputs of the first subtraction unit, and the high-level outputs to the inputs of the decoder connected to the outputs to the address inputs of the memory unit connected to the output with the first group of inputs of the second block of code reading, connected by the outputs of the difference code to the setup inputs of the controlled frequency divider, and output zero reset - to the control input of setting the code of the controlled frequency divider and to the first input of the OR element connected by the output to the first input of the AND element connected by the second input to the output of the pulse generator,

and the output to the signal input of the controlled frequency divider, the output of which is connected to the counting input of the first reversible counter, connected by the control input of the reverse to the output of the difference sign of the second subtraction unit connected by the second group of inputs to the outputs of the first reversible counter, and the zero output with the first the input of the second element And with the first input of the trigger connected by the second input to the output of the first pulse shaper and to the input of the recording control of the buffer register, the direct input to the first input the third element is AND, and the inverse output is to the second input of the second element AND connected by the output to the first input of the second OR element connected to the input of the input register recording control, and the second input through the delay element to the output of the second pulse shaper, the second input of the first the OR element and to the zeroing input of the buffer register connected by information inputs to the low-order outputs of the input register, and outputs to the second group of inputs of the buffer register connected by the spacing code outputs and adjusting the inputs of the subtracter counter output coupled to the input of the second pulse shaper and countable; input - with the output of the third AND gate G2.

A disadvantage of the known device is the reduced performance caused by the digital interpol 31

between the ordinates of the reproduced part of the function.

The purpose of the invention is to improve the speed of the functional converter.

The goal is achieved by the fact that a functional converter containing an input register connected by information inputs to the argument input bus, low-order outputs — to low-order bits of the first group of inputs of the first block of code readout, and high-level outputs — to the inputs of the decoder connected the outputs to the address inputs of the memory unit connected by the outputs to the first group of inputs of the second b. block of code reading connected to the low-order bits of the difference code to the control inputs of the control unit about the frequency divider and zeroing output - to the control input of setting the code of the controlled frequency divider and to the first input of the OR element connected by the output to the first input of the AND element connected by the second input to the output of the pulse generator, and the output to the signal input of the controlled frequency divider, the output of which is connected to the counting input of the first reversible counter, and the first buffer register, introduced a sawtooth generator, multiplying the digital-to-analog converter, the second buffer register, a fashion adder th two second up-down counter, an analog-converter, a register mark, a digital to analog converter and output a summing amplifier connected the first input to the output of the digital to analog converter, and the second input - to the output of multiplying digital to analog converter and the input of analog-to-digital converter connected to outputs with the inputs MSB The outputs of the second buffer register connected by the inputs of the lower bits to the outputs of the first reversible counter, and the outputs to the second group of inputs are second unit of code subtraction and digital inputs of a digital-to-analog converter connected to the gate input, to the output of the OR element and to the trigger input of the saw-tooth generator, the control input of which is connected to the output of the modulo-adder and

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 the reverse control input of the first reversible counter, and the output to the analog input of a multiplying digital-to-analog converter connected by digital inputs to the outputs of the difference code of the second block of code reading, and the control input of setting the code to the gate input of the first buffer register and the output of zeroing of the second block subtracting the codes connected by the output of the difference sign to the first input of the modulo two adder, connected by the second input to the output of the register of the sign, ennogo write control input to the second input of the OR element. control input recording input register and zero output of the first block of code subtraction, the high bits of the first group of inputs of which are connected to the outputs of the high bits of the input register and information inputs of the first buffer, its register, the high bits of the second group of inputs - with the outputs of the first HS of the buffer register , and the lower bits of the second group of inputs - with the outputs of the second reversible counter connected by a counting input to the output of the element I, and the control input of the reverse - to the output of the sign of the difference of the first block subtract audio codes and the sign of the data input register.

FIG. Figure 1 shows a block diagram (a functional converter; Fig. 2 is a graph of a possible change in the argument in the approximation areas of the function.

The functional converter contains a pulse generator 1, an AND 2 element, an OR 3 element, a controlled frequency divider 4, a first reversible counter 5, a second register 6, an argument input bar 7, a first block 8 of code subtraction with a difference of 9 digits and zero output, first buffer register 11, second subtractor 12

0 codes with output of 13 digits of the difference, output of 14 zeroings and outputs of the lower 15 and higher 16 bits of the difference code, memory block 17, decoder 18, second reversing counter 19, register 20 of characters, modulator 21 two (parity control element - oddness), the generator is 22 warm stresses, multiply by

i

| Diffraction converter 23, second buffer register 24, digital input converter 25, analog to digital converter 26, and output-summing amplifier- 27.

Functional Converter works as follows.

.In memory block 17, the ordinate codes f (X |) of the nodal points of the transformation function are recorded, and the zero code is entered first. The higher bits of the argument code, which arrive at the second register 6, are converted by the decoder 18 to the address code, which in the memory block 17 contains the nodal point code of the corresponding value of the conversion function. Block 12 calculates the difference between the ordinate codes of the nodal points, coming from block 17, and the codes of the transformation function, coming from register 24.

The generator 22 generates sawtooth pulses with an amplitude from zero to the maximum value of the working scale, arriving at the analog input of the converter 23. The frequency of the sawtooth pulses

equals f

f 2. n 2

where fo is the reference frequency of the generator 1; ha - counter width 5

and 19,

The polarity of the pulses of the generator 22 is determined by the adder 21 modulo two: the zero signal at the output of the adder 21 corresponds to the pulses of the positive polarity of the generator 22, and a single signal to the pulses of negative polarity.

Using block 8, a comparison time is calculated between the argument code received in the second register 6 and the current, in the process of reproducing the function, the value of the argument code from the outputs of counter 19 and register 11, at which the output corresponding to the received argument is reached at the output of summing amplifier 27.

In the J status state, the reversible counters 5 and 19, the second register 6, the register of 20 characters, the buffer registers 11 and 22 are set to zero. At the same time, by the zero code f (Ho) from the first cell of the memory block 17 and the zero code of the register 24 at the output 14

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the zeroing of block 12 generates a comparison signal. The front edge of the comparison signal is fed through the OR 3 element to the input of the AND 2, 5 element, closing it at the time of setting the dividend transfer factor 4 and the converter 23, and at the gate input of the converter 25, allowing the code from the output of the register 24 to be written, to the control inputs The first divider 4 frequencies, allowing the installation of the division coefficient, to the control input of the converter 23, allowing the recording of the transfer coefficient,

5 and its digital inputs, to the control input of the buffer register 11, allowing the code of the high bits of the register 6 to be written, and to the gate input of the decoder 18, allowing the transfer of the address code to memory block 17. The leading edge of the comparison signal from the zero output of block 8 is fed to the control input of register 6, allowing the transfer of the next value of the argument to

The 25 control input of the register of 20 characters allows the recording of the sign of the difference of the argument codes from the output 9 of the sign of the difference of the block 8.

Consider the work of the converter

.JQ with various options for changing the argument on the approximation in accordance with FIG. 2

When entering the inputs of register 6 of the code of the first value of the argument Xi, the decoder 18, according to the senior bits of the argument code, samples the address of the corresponding value of the function f (X) in the given area of approximation. In block 12, the code difference f (Xi) -f (Xa) is generated, which is fed to the digital inputs of the converter. 23, setting the slope of the sawtooth voltage at its output. The low-order m bits from the outputs 15 of the difference code of block 12 are fed to a frequency divider 4, in which the corresponding division factor is set. At output 9 of block 8 subtraction code, a difference sign is formed between the code of the first argument value received from input register 6 and the code of the zero argument value, whose lower bits come from counter 19, and the higher bits from b5 of the front register 11. The difference sign from output 9 of block 8 is recorded by the high level of the comparison signal from the output 10 of block 8 into the register of 20 characters.

After the input of block 8 of the code of the first argument value at the output 10 of zeroing block 8, the back edge of the comparison signal is delayed by the time required to set the sign of the difference in register 20.

After the function code f (X) arrives at the inputs of block 12, a falling edge of the comparison signal is generated at the output 14 of the delay signal, delayed by the time required to set the difference code f (X) -f (Xo) at the digital inputs of the converter 23 and the division factor of the divider 4 (frequency. On the falling edge of the comparison signal from the output 14 of the block 12, the generator 22 of sawing voltage is started and the element 2 opens, allowing the passage of pulses from the output of the generator 1 of pulses to the count input of counter 19 and through a controlled divider 4 frequencies - on the counting input of the counter 5. A sawtooth voltage is formed at the output of the converter 23, the slope coefficient of which is directly proportional to the difference of the f (Xj) –f (Xo) codes. Thus, the output of the summing amplifier 27 starts linear interprescence of the function at the selected approximation interval.

When the counter code 19 coincides with the low-order code of the first argument value, an impulse comparison signal is generated at the output 10 of the zero reset of the code reading section 8. On the leading edge of the comparison signal, element 2 is closed, the converter 25 from the output of register 24 receives the ordinate code Y, corresponding to the argument code X, the generation of the sawtooth voltage in generator 22 is disrupted and the next argument code value is received in the input register 6. When In this case, the higher bits of the ordinate Y code are formed at the output of the converter 26, the number of bits r of which is equal to

 w-m, ft Hi-m, where n is the number of full bits

code of the ordinate - the number of junior bits

Yin code.,

and the lower bits are determined by the counter code 5.

When the argument code Xi ,, is entered in register 6, at the output 9 of the sign of the difference of block 8, the sign

difference, resulting in the counter 19 goes into the download mode. Due to the high level of the comparison signal from output 10 of block 8, the sign of the code difference is written to the register of 20 characters, which leads to a change in the state at the output of the adder 21, and consequently, to the transfer of the counter 5 to the subtraction mode,. After the receipt of the argument code X ;, at the output 10 of the zeroing of block 8, the leading edge of the comparison signal is formed, on which the AND 2 element is opened and the generator 22 is started, forming a sawtooth pulse of negative polarity. At the output of the converter 23, a sawtooth voltage of negative polarity is formed with the same slope. Thus, at the output of summing amplifier 27, the linear interpolation of the function continues.

When the counter reaches 19 the low-order code of the argument of output 10 of block 8, the comparison pulse signal is formed again. On the leading edge of the Comparison Signal, element 2 is closed, the ordinate code Yj. Is entered into the converter -25, the generation of the sawtooth voltage in the generator 22 is interrupted and the next argument code value is received in the register 6. At the output 9 of block 8, the sign of the difference is formed codes. controlling the reverse of the counter 19 and the state of the adder 21. In this case, the polarity of the sawtooth pulses of the generator 22 changes and the counter 5 switches to the summation mode. On the falling edge of the comparison signal from the zero output of block 8, the element AND opens and the generator 22 sawtooth voltages are started. At the output of summing amplifier 27, the linear interpolation of the function continues. In this case, the division ratio of the divider 4 frequencies and the transmission coefficient at the digital inputs of the converter 23 remain the same and linear interpolation is carried out according to the law determined by the approximating function in the section X - X.

When the ordinate code of the nodal point f (Chl) is reached at the zero output of block 12, the front of the comparison signal is formed, along which And 2 is closed, the code is entered into the converter 25

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ordinates of the node point f (X), the sawtooth voltage is disrupted in the generator 22; the code 11 of the high bits of the argument Xj ,, 2 is equal to the code of the node point of the argument X. On the leading edge of the comparison signal from output 14 of block 12 the higher bits of the argument code are converted by the decoder 18 into the address code, by which the ordinate code of the nodal point f (Xj) is extracted from the memory block 17. In block 12, the difference between the codes f (X2) -f (X /,), which, according to the comparison signal from the output 14 of the block 12, hits the digital inputs of the converter 23, is formed, the slope of the sawtooth voltage from the generator output 22 is determined. Fade digits of the difference code arrive at the comparison signal to a divider of 4 frequencies and set the transmission coefficient in the next section of the approximation. At the output 13 of the block 12, the sign of the difference of the codes is formed, changing the state of the adder 21 and, consequently, the polarity of the sawtooth pulses of the generator 22 and the reverse of the counter 5. On the falling edge of the comparison signal from output 14 of Yalok 12, the duration of which is determined

makes the time necessary to set the codes on the digital inputs of the converter 23 and the transfer ratio of the 4 frequency divider, the AND 2 element is opened and the sawtooth voltage generator 22 is started. At the output of summing amplifier 27, linear interpolation of the function begins at the second approximation interval.

matsii.

In subsequent sections of the approximation of the Converter works in the same way.

Thus, the introduction of hybrid

the interpolation in the functional converter allows using a smaller number of bits during the reproduction of the function, thereby increasing the speed of the converter as compared with the known device, and practically both at the nodal points and within the approximation area, the same as with the counter 5, digital interpolation of the lower bits of the function is performed. This allows the correction of the interpolated function within the approximation segment at the moments of reception of the code of the next argument.

Claims (1)

A FUNCTIONAL CONVERTER containing an input register connected by information inputs to the input bus of the argument, the outputs of the least significant bits with the lower bits of the first group of inputs of the first code subtraction block, and the outputs of the higher bits with inputs of a decoder connected by the outputs to the address inputs of the memory block connected by the outputs , with the first group of inputs of the second block of subtraction of codes connected by the outputs of the least significant bits of the difference code to the installation inputs of the controlled frequency divider, and the zeroing output to the control path of setting the code of the controlled frequency divider and to the first input of the OR element, connected by the output to the first input of the AND element, connected by the second input to the output of the pulse generator, and the output to the signal input of the controlled frequency divider, the output of which is connected to the counting input of the first reversible counter, and a first buffer register, characterized in that, in order to increase the speed of the functional converter, a sawtooth voltage generator is introduced into it, multiplying the digital-to-analog conversion An indexer, a second buffer register, an adder modulo two, a second reversible counter, an analog-to-digital converter, a sign register, a digital-to-analog converter and an output summing amplifier connected by the first input to the output of the digital-to-analog converter, and by the second input to the output of the multiplying digital-to-analog converter and the input of the analog - a digital converter connected by outputs to the inputs of the upper bits of the second buffer register, connected by inputs of the lower bits to the outputs of the first reversible meter, and outputs - to the second group of inputs of the second block of code subtraction and to the digital inputs of the digital-analog converter connected to the gate input, with the output of the OR element and with the start input of the sawtooth voltage generator, the control input of which is connected to the output of the adder modulo two and to the reverse control input of the first reversible counter, and the output to the analog input of the multiplying digital-to-analog converter connected by digital inputs to the outputs of the difference code of the second subtraction block code ov, and the Stop code control input · with the gate input of the decoder, the write control input of the first buffer register and the output of zeroing the second code subtraction unit connected by the difference sign output SU ... 1115069 to the first input of the adder modulo two, connected by the second input to the output of the sign register, connected by the write control input to the second input of the OR element, the input * of the write control of the input register and the zeroing output of the first code subtraction unit, the highest bits of the first group of inputs which are connected to. the outputs of the upper bits of the input register and the information inputs of the first buffer register, the higher bits of the second group of inputs with the outputs of the first buffer register, and the lower bits of the second group of inputs with the outputs of the second reversible counter connected by the counting input to the output of the And element, and the reverse control input - to the output of the difference sign of the first block of subtraction of codes and the information input of the register;