SU1249547A1 - Function generator - Google Patents

Abstract

The invention relates to automation and computing, in particular, to piecewise linear devices. approximations, and can be used in analog-digital computing systems. The aim of the invention is to increase accuracy. The device contains a pulse generator, And and RShI elements, a controlled frequency divider, reversible ordinate counters, abscissas and addresses, abscissa and ordinate memory blocks, two subtractors, a multiplexer, a sign register, a modulo two, a key, an input register, a buffer. register, two digital-to-analog converters, multiplying a digital-to-analog converter, an analog-to-digital converter, a group of elements NOT, an integrator, and a summing amplifier. The goal is achieved by arbitrarily dividing the function into approximation intervals, in particular, when playing back multi-extremal S functions. Within the interval, the correction of the interpolated function is carried out, 2 Il. (/)

Description

ten

The invention relates to the field of automation and computer technology, in particular, to piecewise linear approximation devices, and can be used in analog-digital computing systems.

The aim of the invention is to increase accuracy.

Fig. 1 shows a block diagram of a functional converter, Fig. 2 is a graph of a possible change in the argument in the approximation areas of the function.

The converter contains a generator of 1 pulses, an AND 2 element, an OR 5 3 element, a controlled frequency divider 4, a reversible counter 5 ordinates, an input register 6, an argument input bus 7, the first subtraction unit 8, an output 9 of the difference sign of the block 8, an output 10 zeroed out block 8, output 11 of the operability code of block 8, second subtraction block 12, output 13 of the difference sign 12, output 14 of zeroing block 12, output 15 of the difference code of block 12, block 16 of the ordinate memory, block 17 of the memory ti abscissa, multiplexer 18, reversible counter 19 of argument, register 20 characters, adder 21 modulo two, key 22, multiplying digital to analog converter (UTSAP) 23, a buffer register 24, pervyy.i second digital-to-analog converters (DACs) 25 and 26, respectively, dividing unit 27, an analog-digital converter. (ADC) 28, reversible counter 29 addresses, inte-. grator 30, a summing amplifier 31 and a group of elements HE 32,

12495472

plexor 18. Block 12 determines the code difference between the incoming and previous values of the ordinates,

In division block 27, the slope factor of the interpolating segments on each approximation interval is calculated in accordance with the ratio

Zi i

where u and u 35

X

1-1

Yi-j,

if 1-1

The previous and incoming value of the ordinates from block 12, and X | - the previous and incoming value of the abscissa from block 8,

Counter 5 performs digital interpolation of the lower bits of the transformation function, which allows correction of the interpolated function within the approximation area at the moments of reception of the code of the next argument.

At the output of the integrator 30, a linearly varying voltage is generated with an amplitude from zero to the maximum value of the working scale, which is fed to the analog input of UCAP 23, and the time constant of the integrator 30 is determined from the condition

thirty

 Int

. g v., ,,

f V.

X so

where d is the reference frequency of the generator; m is the counter size of the counter 5,

V, - the maximum value of the working inis "

abscissa scales.

V,

(X,

- -V. )

- minimal

 abscissa quantization step (ra-. ven to the minimum approximation interval),

The procedure works as follows,

In block 16 of the ordinate memory, the ordinate codes of the nodal points of the transform function f (x) are entered, In abscissa memory block 17, the abscissa codes of the nodal points of the transform function are entered, and the zero cell is entered into the first cell of the 16 and 17 memory units By output code reversible counter, 29, the width of which is determined by the number of nodal points stored in IB blocks 17 and 16, contains the abscissa and ordinate codes of the corresponding value of the transform function.

Subtraction unit 8 calculates the code difference between the incoming and the previous abscissa values or arguments depending on the signal. coming to the address input multi

„

0

5 20

Zi i

where y and y X

1-1

Yi-j,

if 1-1

The previous and incoming value of the ordinates from block 12, and X | - the previous and incoming value of the abscissa from block 8,

Counter 5 performs digital interpolation of the lower bits of the transformation function, which allows correction of the interpolated function within the approximation area at the moments of reception of the code of the next argument.

At the output of the integrator 30, a linearly varying voltage is generated with an amplitude from zero to the maximum value of the working scale, which is fed to the analog input of UCAP 23, and the time constant of the integrator 30 is determined from the condition

thirty

 Int

. g v., ,,

f V.

X so

where d is the reference frequency of the generator; m is the counter size of the counter 5,

one,

V, - the maximum value of the working inis "

abscissa scales.

V,

(X,

- -V. )

- minimal

 abscissa quantization step (ra-. ven to the minimum approximation interval),

The polarity of the output voltage of the DAC 26 is determined by the modulator 21 modulo two: a zero signal at the output of the adder 21 corresponds to a voltage of a positive polarity, and a single signal to a voltage of negative polarity.

Using block 8, the moments of comparison are calculated between the argument code received in the input register 6 and the value of the argument code from the output of the counter 19, at which is the current value during the playback of the function. The output of summing amplifier 31 reaches the value corresponding to the input argument.

In the initial state, the reversible. Counters 5, 19, and 29, the input register

6, the register of 20 characters, the buffer register 24 is set to zero. At the same time, zero codes are extracted from the zero code of the counter 29 of the addresses from the first cells of memory blocks 16 and 17, and a zero signal is generated from the zero code of the register 24 at the zero output of the block 12. The leading edge of the comparison signal goes through the IL 3 element to the input of the AND 2 element, closing it at the time of setting the divider 4 transmission frequency and UTsAP 23, storing the DAC 25 gate input, allowing recording of the code from the register 24 output, and to the initial position input integrator 30, setting a zero initial value at its output, to the input of the gating of dividing unit 2, permitting the calculation of the transfer factor of the 4 frequency divider and UCAP 23, to the address input of the multiplexer 18, allowing the connection to the output unit 8 of the memory block 17 and, on the strobe input of the DAC 26, allowing the code from the output 11 of block 8 to be written, and to the counting input of the counter 29, transferring it to the next state. The leading edge of the comparison signal from output 10 of block 8 goes to the gate input of register 6, thereby allowing reception of the first value of the argument, and to gate input of the register of 20 characters, allowing the sign of the difference of the argument codes from output 9 of block 8 to be written.

Consider the operation of the converter with different variations of the change; argument on the plot of approximation in accordance with figure 2.

According to the counter code 14 of the address, blocks 16 and 17 extract the ordinate codes y and abscissa X of the first approximation area. At the same time, the multiplexer 18 connects the output of memory block 17 to the output of a decremented block 8, and the output 11 of block 8 calculates the difference between the codes X -X g between the values of block 17 and counter 19, and the output 15 of block 12 calculates the difference y between the values of block 18 and buffer register 24. Division 27 calculates the code

arriving at the digital input ZSHAP 23

setting the slope of the linearly varying voltage on it in the {1 going. Younger m bits from the output of block 27 are fed to the 4 frequency divider, in which

0

five

0

five

the corresponding division factor is reduced. In the DAC 26, the return code of the abscissa difference (x -, determining the integration time of the integrator 30 in this approximation area) is entered.

After the ordinate code of the first block of approximation y arrives at the input of block 12, output 14 of the block 12 produces a falling edge of the comparison signal delayed by the time required to set the code from the output of block 27 on the digital inputs of UCAP 23 and the split factor of the 4 frequency divider. On the falling edge of the comparison signal from the output 14 of the block 12, the multiplexer 18 switches to the output of the reduced block 8 the output of the input register 6.

When entering the inputs of register 6 of the code of the first value of the argument at the output 9 of block 8 of the subtraction, the difference sign between the code of the first value of the argument from register 6 and the code of the zero value of the argument coming from the output of the counter 19 is formed. The sign of the difference from the output 9 of block 8 is recorded by the high level of the comparison signal from output 10 of block 8 to the register of 20 characters.

After the input of block 8 of the code of the first argument value x, the zero edge of output 8 of block 8 forms the falling edge of the comparison signal, which is delayed by the time required to set the sign of the difference in register 20 and switch through the switch 22 of the reference voltage corresponding to polarity DAC 26. On the falling edge of the comparison signal from output 10 of block 8, the integrator 30 is started and the element 2 is opened, allowing the pulses to go from the output of the pulse generator 1 to the counting input of the counter 19 and through the controlled divider 4 pilots at - to the count input of the counter 5..Na output of the integrator 30 is linearly formed a varying voltage from zero to a maximum working cupboard. In this case, the integration time of the integrator 30 is determined by the difference of the codes (x - sG). The slope coefficient of the linearly varying voltage at the output of UCAP 23 is directly proportional to the ratio

-H.

X

, - X.

Thus, at the output of the summing amplifier 31, linear interpolation of the function begins at the selected approximation interval.

If the counter code is 19 and; the code of the first argument value

the zero value of the integrator 30 is set and the next value of the argument code is received in register 6. At output 9 of block 8, the sign of the difference between codes X., j - J controlling the reverse of counter 29 and the state of adder 21 is formed. 21, the counter 5 enters the summron mode. The output 10 of the zeroing of the block 8 shows no codes. A pulse comparison signal is generated. On the leading edge of the comparison signal, the vanishing element 10 is closed and the polarity of the reference-AND 2 changes in the DAC 25 from the output of the 24 register voltage of the DAC 26. On the back is the ordinate code corresponding to the front of the comparison signal from the zero output of block 8 opens element 2 and the launch of the integration

The argument code is set to zero, the integrator 30 is set to zero, and the next torus 30 is received. At the output of the summing signal — the argument code values in the input 31, the linear in other register 6 continues. terpci of function. At the same time, the division factor of the divider 4 frequencies and the coefficient of transmission to digital inputs

dy of ordinate code y. are formed at the output of the ADC 28, the number of bits of which is 1 n - m, where n - if –20 dax of UCAP 23 remains the same and the number of bits of the full ordinate code y. , m is the number of the least significant bits of the ordinate code y, determined by the counter length 5.

When an argument code arrives in register 6 at output 9, the sign of the difference of block 8 changes the sign of the difference by which the sign of the reverser changes

Neutral interpolation is carried out according to the law determined by the approximating function on the segment x - x. .

When the ordinate reaches the nodal point code

 f (x)

exit 14

block 12, the leading edge of the comparison signal is formed, according to which the element And 2 is closed in the DAC 25, the ordinate code of the nodal point is entered

sa counter 29. On a high level

block 12, the leading edge of the comparison signal is formed, according to which the element And 2 is closed in the DAC 25, the ordinate code of the nodal point is entered

the comparison signal from the output 10 of the block 8 JQ (x), the zero-sign of the code difference is set is written to the character register 26, as a result of which the counter 19 goes into the subtraction mode and the output state of the sum of the initial value of the integrator 30 changes, the counter 29 is transferred to next state, multiplexer 18 connects to the input of the block to be reduced

the initial value of the integrated 30, the counter 29 is transferred to the next state, the multiplexer 1 connects to the input of the reduced b

Matora 21. According to the output code, totalizer– 8 output of memory block 17. By code

21, the counter 5 is switched to the forward mode, and a negative voltage reference voltage is connected to the DAC 26 via a switch 22. After the code arrives, the argument: at the output 10 of zeroing block 8, the leading edge of the comparison signal is formed, in which element 2 is opened and the start of integrator 30 is formed, forming linearly varying voltage, negative polarity. At the output of UCAP 23, a linearly varying negative polarity voltage is formed with the same slope. Thus, the output is summed- ,. The booster amplifier 31 continues by interpolating the function.

When the counter 19 reaches the argument code x, the output pulse of the comparison signal 55 is again generated at the output 10 of the unit 8. On the leading edge of the comparison signal, the element And 2, 13 of the D / A converter 25 closes the ordinate code. ,

counter 14 addresses from blocks 16 and memory, ordinate codes and X-axis abscissas are extracted from the second portion of the approximation. At the output of 11 block 8

is the difference of the x codes. - x between the values of block 17 and counter 19 at output 15 of block 12 - difference y y, j - between the values of the block and the buffer register 24. In the high level dividing block, the comparison signal from the output 14 of block 12 gives you a code

.IL.

X

-z-Zi X.

-g 1

arriving at the digital inputs of the UCA 23, determining the slope of the linearly measuring voltage at its output. The low m bits of the block output go to a divider of 4 frequencies, applying the corresponding division factor. In the D / A converter 26, different codes (x - x) are output from the output 11 of the block. At the output 13 of the block 12,

the zero value of the integrator 30 is set and the next value of the argument code is received in register 6. At output 9 of block 8, the sign of the difference between codes X., j - J controlling the reverse of counter 29 and the state of adder 21 is formed. 21, the counter 5 goes into the summation mode and the polarity of the reference voltage of the DAC 26 changes. On the back

the polarity of the reference voltage of the DAC 26. and

the edge of the comparison signal from the output 10 of zeroing the block 8, the element 2 is opened and the integration

The division frequency divider 4 frequency and the transmission coefficient on the digital inputs of UCAP 23 remain the same and

dakh UCAP 23 remain the same and

Neutral interpolation is carried out according to the law determined by the approximating function on the plot x - x. .

When the ordinate reaches the nodal point code

 f (x)

exit 14

block 12, the leading edge of the comparison signal is formed, according to which the element And 2 is closed in the DAC 25, the ordinate code of the nodal point is entered

(x), the zero initial value of the integrator 30 is set, the counter 29 is transferred to the next state, the multiplexer 18 connects to the input of the decremented block

counter 14 addresses from blocks 16 and 17 of memory are extracted ordinate codes y and abscissa X- of the second approximation area. At output 11 of block 8, the difference in the x codes is calculated. - x between the values of block 17 and counter 19, and at output 15 of block 12 - the difference between the codes y, j - between the values of block 18 and the buffer register 24. In block 27 dividing by the high level of the comparison signal from output 14 of the block 12 computed code

.IL.

X

-z-Zi X.

-g 1

arriving at the UCAP 23 digital inputs, the slope of the linearly varying voltage at its output is determined. The younger m bits of the output of the block, 27 arrive at the divider 4 frequencies, mouth. Pour the corresponding division factor. In the DAC 26, the code difference (x - x) is output from the output 11 of the block 8. At the output 13 of the block 12,

the sign of the difference between the codes y, y, the changing state of the adder 21, and hence the reverse of counter 5, and the polarity of the reference voltage of the DAC 26 "On the back front of the comparison signal from output 14 of block 12, the duration of which is determined by the time required to set the codes on the digital inputs of UCAP 23 and the transfer coefficient of the 4 frequency divider, element 2 is opened and the integrator 30 is started up. At the output of the summing amplifier 31, linear interpolation of the function begins at the second approximation interval.

In subsequent sections, the device works in a similar way.

: Fo. rmula of invention

Functional converter containing a pulse generator, AND element, controlled frequency divider, reversible counter of the argument, the reverser is connected to the input of the argument of the functional converter, the sign output of the first subtraction unit is connected to the information input of the sign register, the output of which is connected to the first modulator two, the output and the second input of which are connected respectively with the control input of the reverse reversible ordinate counter and the output of the sign of the second subtraction unit S output zero which is connected to the second input of the OR gate, the output buffer register to the information input of the first transducer tsif- roanalogovogo soedi-. not the input of the subtracted second subtraction unit, the input of which is decremented is connected to the output of the ordinate memory block; abscissa memory

large ordinate counter, buffer re- 35 i dividing unit, group of elements NOT,

gist, element OR, analog-digital

35

converter, multiplying digital-analog converter, input register, two subtraction blocks, sign register, modulo two, block, ordinate memory, first tsifroanaloj converter and summing amplifier, the output of the pulse generator connected to the first input of the element And, the output of which is connected to the counting input of the reversible argument counter and the information input of the controlled frequency divider, the output of which is connected to the counting input of the reverse ordinate counter, the output of which is connected to the input of ml the higher bits of the buffer register, the input of the higher bits of which is connected to the output of the analog-digital converter, the input of which is connected to the output of the multiplying digital-to-analog converter and the first input of the summing amplifier, the output and second input of which are connected respectively to the output of the functional converter and the output of the first digital-analog converter, whose gate input is connected to the output of the OR element and the second input of the AND element, the first input of the OR element is connected

40

45

50

55

the second digital-to-analog converter, integrator, key and reversible address counter, the outputs of the input register and the abscissa memory block are connected respectively to the first and second information inputs of the multiplexer, the output of which is connected to the input of the decremented first subtraction unit, the code output of which is connected to the input of the splitter splitter the input of the dividend and the output of which are connected respectively with the code output of the second subtraction unit and the digital input of the multiplying digital-analog converter, the output of the small Shih bits and dividing the input gating unit are connected respectively to the input specifying coefficient controllable frequency divider and the output of the second subtractor zeroing,

The zeroing code of which is connected to the gate input of the second digital-to-analog converter, the output and information input of which are connected respectively to the information input of the integrator and the inputs of the elements of the NOT group whose inputs are connected to the corresponding bits of the code output of the first power supply unit whose output of the sign is connected to the control input by reversing the reverse address counter, the counting input of which is connected to the output of the delta block sign by the zero output of the first subtraction unit, by the gate input neither the sign register and the input register strobe input, the information input

15

ten

49547-8

which is connected to the input of the argument of the functional converter, the output of the sign of the first subtraction unit is connected to the information input of the register of the sign, the output of which is connected to the first input of the modulo-two adder, the output and the second input of which are connected respectively to the control input of the reverse reversible ordinate counter and the output of the second of the subtraction unit S, the zeroing output of which is connected to the second input of the OR element, the output of the buffer register with the information input of the first digital-analogue converter with di-. not connected to the input of the subtracted second subtraction unit, the input of which is decremented is connected to the output of the ordinate memory unit; the input of the subtracted first subtraction unit is connected to the output of the reversible argument counter, о t20

distinguished by the fact that

,

0

five

0

five

the second digital-to-analog converter, integrator, key and reversible address counter, the outputs of the input register and the abscissa memory block are connected respectively to the first and second information inputs of the multiplexer, the output of which is connected to the input of the decremented first subtraction unit, the code output of which is connected to the input of the splitter splitter the input of the dividend and the output of which are connected respectively with the code output of the second subtraction unit and the digital input of the multiplying digital-analog converter, the output of the small Shih bits and dividing the input gating unit are connected respectively to the input specifying coefficient controllable frequency divider and the output of the second subtractor zeroing,

The zeroing code of which is connected to the gate input of the second digital-to-analog converter, the output and information input of which are connected respectively to the information input of the integrator and the inputs of the elements of the NOT group whose inputs are connected to the corresponding bits of the code output of the first power supply unit whose output of the sign is connected to the control input the reverse of the reverse address counter, the counting input of which is connected to the output of the sign of the division unit and the address input of the multiplexer, the input of the control of the reverse the reversible counter of the argument is connected to the output of the sign register, the output of the reversible counter of the address is connected to the address inputs of the abscissa and ordinate memory blocks, the output of the modulo-two is connected to the control input of the key. the positive and negative inputs of which the reference voltages are connected to the input of the functional converter, the output of the knockout is connected to the input of the second polarity setting (|

Fig 2

Editor L.Gratillo Order 4327/51

Compiled by A. Zorin Tehred V. Kadar

Proofreader M. Demchik

Circulation 671 Subscription

VNIIPI USSR State Committee

On affairs of inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

Proofreader M. Demchik

Claims (1)

Claim 20 Functional converter, containing pulse generator, AND element, controlled frequency divider, reversible argument counter, reversible ordinate counter, buffer re- ₂ 5 histr, OR element, analog-to-digital converter, multiplying digital-to-analog converter, input register, two subtraction blocks, register sign, adder modulo two, ordinate memory block, the first is a digital-to-analog converter and a summing amplifier, and the output of the pulse generator is connected to the first input. And element, the output of which is connected with a counting input of a reversible counter of argument ³⁵ and an information input of a controlled frequency divider, the output of which is connected to a counting input of a reversing ordinate counter, output 40 of which is connected to the input of the lower bits of the buffer register, the input of the highest bits of which is connected to the output of the analog-to-digital converter, the input of which is connected to the output of the multiplying digital-to-analog converter and the first input of the summing amplifier, the output and second input of which are connected respectively to the output of the functional converter and the output of the first digital-to-analog converter, the gate input of which is connected to the output of the OR element and the second input of the AND element, the first input of the OR element is connected ene yield zeroing You are a first block ⁵⁵ subtracting, entrance gating input gating mark and the input register having an information input coupled to an input of a functional argument converter, the output of the first subtracting unit is connected to the sign of the sign data input register, whose output is connected to a first input of an adder modulo two _g output and the second input of which are connected respectively to the control input of the reverse of the ordinate counter and the output of the sign of the second subtraction block, the output is reset whose name is connected to the second input of the OR element, the output of the buffer register with the information input of the first digital-to-analog converter is connected. _the input of the subtracted second subtraction block, the input of which is reduced is connected to the output of the ordinate memory block, the input of the subtracted first subtraction block is connected to the output of the reverse argument counter, which is characterized by the fact that, in order to increase accuracy, a multiplexer, block abscissa memory 'division block, group of elements NOT, second digital-to-analog converter, integrator, key and a reversible address counter, the outputs of the input register and the abscissa memory block being connected respectively to the first and second information the input inputs of the multiplexer, the output of which is connected to the input of the reduced first subtraction unit, the code output of which is connected to the input of the divider of the division unit, the input of the dividend and the output of which are connected respectively to the code output of the second subtraction unit and the digital input of the multiplying digital-to-analog converter, the low-order output and the gating input the division block are connected respectively to the input of the task of the coefficient of the controlled frequency divider and the zeroing output of the second subtraction block, the zeroing output I connected to the gate input of the second digital-to-analog converter, the output and information input of which are connected respectively to the information input of the integrator and inputs of elements of NOT a group whose inputs are connected to the corresponding bits of the code output of the first subtraction unit, the sign output of which is connected to the control input of the reverse address counter , the counting input of which is connected to the output of the division block sign and the address input of the multiplexer, the reverse control input is a reverse counting the argument handler is connected to the output of the sign register, the output of the reverse address counter is connected to the address inputs of the abscissas and ordinates, the output of the adder is modulo two connected to the control input of the key, the inputs of the positive and negative reference voltages of which are connected to the input of the functional converter, the key output is connected to the input of the polarity reference of the second digit5 of the analog converter, output! The OR element is connected to the installation input of the integrator, the output of which is connected to the analog input of the multiplying digital-to-analog converter.