SU1707766A1 - Echo compensator - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve noise immunity. The device contains a matching unit 1, a switch 2, a DAC 3 and 10, an A / D converter 4, a shaper 5 code combinations, a memory b block, a control pulse generator 7, an emitter 8. an adder 9. The goal is achieved by inserting registers 11 and 12 of the key 14 In memory block 6, pulsed echo path response counts are recorded. In the process of signal transmission, the transmitted signal is summed with the recorded signals and subtracted from the echo signal. 2 Il. e Ј v | vj o o

Description

The invention relates to telecommunications and can be used in devices for duplex transmission of binary or speech signals.

Known echo canceller, containing a delay line with taps, multipliers, correlators, adder and subtractor. and the taps of the delay line are connected to the first inputs of the multipliers, the outputs of which are connected to the inputs of the sucmator, the output of which is connected to the input of the reader, the output of which is connected to the inputs of the correlators, the outputs of the matrix x are connected to the second inputs of the multipliers.

A digital echo canceller is known, containing the first and second nonlinear elements, the first and second registers, the adder, the subtractor, the multiplier, the digital-to-digital converter, the first: second and second analog-to-digital converters, the output of the first anlose digital-to-0 converter connected to the input and output of the first register, the input of the second nonlinear element and the first input of the multiplier, the output of which is connected to the first input of the second analogue -;.; -. 1 of this converter, and the output from the digggm to the input of the c. vattel and the entrance of the first non-linear elomang; The output is co-connected with: -. input / .omultiply / tel, the second of which is connected to the GHRD of a nonlinear e output element is connected to the .jM output of the adder, the second input of which is connected to the second input of the actual output and the output of the .rtc register, in .--. LId which is connected to the output of summa-rg

The disadvantage of the local exams is torgv rvpchets complexity. K kakie zkhok to mpv sztory soderhat either a large v-layer of multipliers, or one fast-acting multiplier, difficult in practical implementation.

The closest to the present invention is an echo canceller, comprising a matching unit, a first and second digital-to-LOGO converter, a series-connected digital-to-digital converter and a subtractor. a switch, a memory unit, an adder, a generator controlling it, pulses, a control unit and drivers of code combinations whose output and the output of the matching unit are connected respectively to the first and second information inputs of the switch whose output is connected to the address input of the memory block and to the input of the first digital-analog converter, the output of which

connected to the echotragg and to the information input of the analog-digital converter, the information input of the memory unit is connected to the output of the analog-digital

the converter and the first input of the calculator, the output of the control unit is connected to the control input of the switch, and the output of the generator of control pulses is connected to the control inputs of the unit

0 matching, analog-digital converter and driver code combinations.

The disadvantage of this echo canceller is the low noise immunity due to

5, a large error of undercompensation at the output of the device arises due to the influence of transients in the echo path, which are not taken into account when training the device.

0 The aim of the invention is to improve the noise immunity of the echo canceller. The goal is achieved by the fact that in the echo canceller containing the matching unit, the first and second digital-to-analog

5 a converter, serially connected analog-to-digital converter and subtractor, a switch, a memory unit, an adder, a generator of control pulses, a preparation unit and a driver of code combinations, the output of which, as well as the output of the matching unit, are connected accordingly to the first and the second ICF-MZTs-1SNNOM inputs of the switch, the output of which is connected to the address input of the memory block and to the input of the first digital-analogue converter, the output of which is connected to the extract and to the information input of the English-digital th converter, information input of the block

Memory 0 is connected to the output of the digital-to-digit converter and to the first input of the subtractor, the output of the control unit is connected to the control. The switch input, and the output of the control pulse generator unit are connected to the control inputs of the matching unit, the analog-digital converter and the driver of code combinations, the first and second memory registers are additionally

0 connection connected between the input of the first digital-to-analog converter and the switch output connected to the first address input of the memory block and the information input of the first memory register, the taps and the output of which are connected respectively to the subsequent address inputs of the memory block in order of increasing numbers , the output of the analog-digital converter connected to the last information input of the block

The memory is connected to the information input of the second register of the memory. The outputs and output of which are connected to the previous information inputs of the memory unit in order of decreasing their numbers, all the outputs of which are connected to the inputs of the adder, the output of which is connected to the second input of the readout device, the output of which is connected to the input of the second digital-to-analog converter, which control the inputs of the first and second memory registers are connected to the output of the control pulse generator and the input of the control unit, the ator and the third output of which are connected respectively to the control input of the memory blocks and the control input house key.

Comparative analysis with a well-known story. that the proposed device is distinguished by the presence of new blocks: two memory and key registers, as well as their networks with residual blocks.

A comparison of the proposed solution with other technical solutions shows that the keys of the electrical signal boxes are widely known, and the memory registers as delay elements are used in digital dhs compensators, which are indicated by their PSM / us-mode. in known echoes-ss-delay elements are applied; SRI C 5b.STRODEYSTG uRushchem leremchszhitegmm that lead / gu ok ukoeno above, to the complication of the echo tendency. In the gedpageem ecxmgens torus of a hedgeball player of 5 m, they will be called in combination by a pam block. C - ,. what makes it possible to realize p. -higher - and .e noise immunity without g.rimo nani irreducible users, which ensures a fairly simple practical implementation of echok - pens9tgch

FIG. presents futsional; -zz electric s / emz device: on fi .2 - voltage diagrams, which show the operation of the device

The echo canceller based on the memory block (Fig. 1) contains matching block 1, switch 2, first digital-to-analog converter 3, analog-to-digital converter 4. shaper 5 of code ksmb1. memory unit 6, control pulse generator 7, subtractor 8, accumulator 9, second digital-to-analogue converter 0, first 11 and second 12 memory registers, control unit 13, key 14.

The ecxpenser based on the memory block works as follows.

Before the session, the same. As in the well-known, training of the echo canceller is carried out taking into account the parameters of the connected echo path. The response signal of the subscriber during training should be absent. The essence of learning is as follows.

According to the signal of the control unit 13, the switch 2 connects the output of the shaper 5 5 code combinations to the input of the first 11 memory register and the first address input of the memory unit 6 Shaper 5 code combinations form the binary combinations Xgl. where m is 0, 1, 2, .. ,, which is characteristic also for the well-known, but in contrast to the exudative progression of the indicated THROTTLE combinations is less than the frequency of hepatopra 7 C times, where C is the frequency division factor of the incoming For5 worldlord 5 divider. For example, X0 OO1 (figure 2, a). At the time t 0, the key 14, by the signal of the control unit 13, is discovered by a time equal to the repetition period T of the generator pulses 7 arriving at the control inputs of the matching unit 1, which has a wide transducer 4, the first 11 and the second 12 memory registers. Thus, the first 3 digital-to-analogue transform of the tel receives a binary pulse with the level 001 and duration T (Fig. 2, b), which from the output of the specified digital converter in the analogue guide enters the echo path and simultaneously to the input

0 an analog-to-digital converter 4, and the pulse shape is distorted due to the influence of transients in the extract (Fig. 2c). Instant value of such a pulse to an arbitrary

5, the moment of time is determined by the overlay formula known from the theory of eletriches / circuits

X (t)) -t -,: t-T) (1) where h (t) is the echo-response reaction to a single

0 Function.

Analog-to-digital converter 4 converts the analog signal X (t) into binary Xn, where n 0. 1, 2, ..., which is also characteristic of the known-. However, unlike

5 from the known control signal RECORDING from the control unit 13 to the control input of the memory unit 6 arrives with some delay relative to the moment of opening the key 14 (Fig. 2, d). Time

0 delay is equal to (N -1) T. where N is the number of information (address) inputs of memory block 6.

Binary combinations from the output of the analog-to-digital converter 4, corresponding to the digital readings of the fuzzy (Fig. 2, c) pulse, are advanced along the memory register 12, and at the time of the arrival of the RECORD signal, the first readout time is applied to the first information input of the block used memory

the second countdown to the second input, etc. Simultaneously and synchronously, the code combinations from the output of the former 5 are promoted along the first register 11 of the memory. But since the code combination at the output of the generator 5 does not change during the time interval from t 0 to t (N - 1) 7 (Fig, 2, a), then at the moment of arrival of the RECORD signal on all address inputs of memory block 6 the same code combination X0 001 appears. According to the RECORD signal, information attached to the information inputs of memory block 6 is recorded at address 001, the first time counting of the blurred (Fig.2, c) pulse is recorded in the first information area memory block 6 (how it is attached to the first information input), analogs but the second count is recorded into the second area informetsi- onnuyu etc Then, at time t PT reme- audio generator 5 generates the following codeword Xi - 010 (2, s). and in the same way, samples of the blurred (Fig. 2, c) pulse are recorded in all information areas of memory block 5 at address 010. So it is, until Shaper 5 enumerates the used days of transmission. ,: cP1: combinations.

Thus, the result of the training process is recorded in the information area 1 of the block b). The following information is recorded:

by address X0 is written X0h (0); by Ј. ;;: e - v Xi is written Xih (O): (2)

by - ;; p; ss X- is written CT (0). E information area 2 Write / .- next :: information: 40 at address / X0 is recorded (T) -h (

at address Xi, (T) -h (0) is written:

(3)

at XT is written (T) -h (0).

Anzlo: In the information area N, the following information is recorded:

at X0, write X0 {h (N-1) TT-

-h (N-2)

at address Xi is written Xi {h (N-1) TJ-h | i J-2) (4)

at address Xm, Xm {h (N-1) T} - -h (N-2) is written.

The division factor C of the frequency divider included in the former 5 must be chosen taking into account that by the time each

0 5 0 5 0

five

0

five

0

five

the subsequent impulse transients from previous impulses (figure 2c) basically ended. For example, if the echo canceller is designed to work with subscriber lines of small and medium length, the duration of transient processes (impulse response) which, as is known, does not exceed (4-6) ms, it is advisable to choose C 64, then for a period T 125 μs of generator pulses

7, the interval between adjacent pulses is equal to ST 8 ms. and the training time with the number of code combinations m 256 of the driver 5 will be 256-8 8 s.

After completion of the learning process, the key 14 is set to the constantly open state by a signal from the control unit 13, and the switch 2 connects the output of the matching unit 1 to the input of the first 11 memory register and the first address input of the memory unit. In the data transfer mode, the RECORD pulses are not received to the memory block 6, the memory block operates in the data storage and reading mode. The signal X (t) from the output of the message source is fed to the input of the matching unit 1, which is converted to binary Form Xi. where i 0, 1, 2, ..., and goes through the switch 2 to the first address input of the memory block 6 and to the information input of the memory register 11. At the same time, the same signal passes through the public key 14 to the convergence of the analog to analog converter 3. D which is converted to analog form, is fed to the information input of the analog-digital converter &, which is converted back to digital form and digitally from the output of the digital-to-digital converter enters the first input of the subtractor V. which is also characteristic of the famous. The second input of the same subtractor receives a digital signal from the output of the adder 9, which in the ideal case (with an infinite number of taps of memory registers 11 and 12 and, accordingly, the infinite information capacity of memory block 6) and in the absence of a response signal from the subscriber is an exact copy of the digital the signal from the output of the digital converter 4. and the signal at the output of the subtractor 8 is zero.

8 to the real device, the indicated signal is not equal to zero, since there is some undercompensation error due to the influence of transient processes in the echotrack, however, with an increase in the number of registers of memory registers 11 and 12 and a corresponding increase in the number of information areas of memory 6, this the error is reduced, which is an advantage of the device being offered as compared with the known one.

We take a closer look at the process of echo compensation. At a randomly selected discrete point in time from the beginning of the transfer of information t LT signal X | from the output of block 1, the matching is distributed to the address inputs of memory block 6 as follows:

at the entrance to hell - 1 count XL;

ad entry - 2 count XL-i; (5)

ig. the input ad - N is the count XL-N-M- Substituting the values of the data read from block 6 of the data from expressions (2). (3) and (4) in expression (5) and summing them, we find the value of the signal at the output of the adder 9

Ui-XL-NHnKN-iyn-t-fXL-N

- XL-N-iM (N-2) T + (XL-N + 3 - XL-N + Z) xxb (N-3} Tl + + (XL-XL-i) h (O) -XL-N -ih (N-1) (XL-N + H-Ii 1

-XL-N4i (N-l-1) T.

The signal Xi, as indicated above, is sent through the key 14 to the input of the first digital-to-analog converter 3, from the output of which, in analog form, is fed to an echotct and simultaneously with the response signal of the subscriber is fed to the information input of the analog-digital converter 4. Signal value at the output of the known -digital converter 4 at a discrete point in time t IT is determined by the shape of the overlay

U-Xr, h (LT) + T (Xi-Xi-i) hI (L-l) T + Yi, (7)

i 1

where YI is the subscriber signal count.

As a result of subtracting the right-hand sides of the expressions (7) and (6) from each other, we find the difference signal at the output of the subtractor 8

Iraz - U - O. - Xoh (LT) + Ј (Xi - Xti) x

I 1

x h (L-l) T + Yi - (N-1) T - V () - XL-N + i) h (N-M) T i 1

- Xoh (LT) + (X. - Xi-i) h (L- i) Tl i 1

(N-1) Yi- 6+ Yi. (8)

where (5 is the error of undercompensation.

From the expression (8) it follows that the error of the undercompensation is

5- X0h (LT) -XL-Nh (N-1) 1

+ I (Xi - Xi-i) h (L-I) T.

(9)

5From the theory of electrical circuits, of course. that h (t) with increasing ti is, according to a law close to. exponential, and therefore, by increasing N, it is possible to reduce the undercompensation error and increase

, Q noise immunity of echo canceller. despite the influence of transients in the echo path.

Claims (2)

The invention claims echo canceller. containing successively connected matching unit and switch, the second information input of which is connected to the output of the code generator, the input of which is connected to the output of the generator 2Q control pulses and with the control inputs of the matching unit and the analog-to-digital converter, whose information input is connected to the output of the first digital-to-analog converter and sub 25 keys to the echo path, the first output of the control unit is connected to the control input of the switch, whose output is connected to the first the address input of the memory block whose information input is connected to The Q output of the analog-to-digital converter and the first input of the subtractor, as well as the adder and the second digital-to-analog converter, are characterized in that. In order to improve interference resistance, the first and second memory registers and a key, the output of which is connected to the input of the first D / A converter, are entered into it, and the key input is connected to the output of the switch and in4 (1 formational input of the first memory register, whose outputs connected to 2 ... N with the address inputs of the memory block, respectively, the output of the analog-digital converter is connected to the Nth information input of the memory block and connected to the information input of the second memory register, the outputs of which are connected to 1, .. (N-1 a) information inputs of the memory block, the outputs of which are connected to the corresponding inputs of the adder, the output of which is connected to the second input of the calculator, the output of which is connected to the input of the second digital-analog converter, and the control inputs of the first and second its memory registers are connected to the output of the control pulse generator and the input of the control unit, the second and third outputs of which are connected respectively to the control input of the memory block and the control input of the key. S Sleep about CT