RU1818694C - Condenser - Google Patents

Abstract

The invention relates to the field of telecommunications, in particular to wire communication technology. The purpose of the invention is to increase the noise immunity to quantization of analog-to-digital converters and also to the interference present in the echo path at the time of training by recording binary combinations obtained by training the device in the memory unit as a result of multiplying the samples of the echo path impulse response by a certain factor. The echo canceller contains a matching unit 1, a first switch 2, a first 3 and a second 10 digital-to-analog converter, an analog-to-digital converter 4, a subtractor 8, a code combination generator 5, a memory unit 6, a control pulse generator 7, an adder 9, the first 11 and the second 12 memory registers, control unit 13, key 14. New in the device is the additional introduction of the multiplier t5 and the second switch 16, the highest bit of the data bus at the input of which has a logic level V1, and all other bits of the specified bus have ur Wen logical O. 2-yl.

Description

The invention relates to telecommunications and may find application in devices for duplex transmission of binary or voice signals.

The aim of the invention is to increase the noise immunity of the echo canceller to the quantization noise of the A / D converter, as well as to the interference present in the echo path at the time of training.

In FIG. 1 is a functional electrical diagram of a device; in FIG. 2 - stress diagrams explaining his work.

The echo canceller (Fig. 1) contains a block

I matching, first switch 2, first digital-to-analog converter 1, analog-to-digital converter 4, code combination generator 5, memory unit 6, control pulse generator 7, subtractor 8. adder 9V second digital-to-analog converter 10, first

II and second 12 memory registers, control unit 13, key 14, multiplier 15, second switch 16.

The echo canceller works as follows.

Before the work session, as with the prototype, training of the echo canceller is carried out taking into account the parameters (input impedance) of the connected echo path. It happens as follows.

By the signal of the control unit 13, the switch 2 connects the output of the code combination generator 5 to the input of the first 11 memory registers, the first address input of the memory block, the first inputs of the second switch 16 and the multiplier 15.

By this signal, the second switch 16 connects its second input, on which there is a binary number 100 ... 02 (the index 2 in the lower part of the number indicates the base of the number system), with the input of the key 14, Code combination generator 5, as in the prototype , forms binary combinations Xm, where M 0, 1.2 ... The sequence of each code combination Xm is CT, where C is the coefficient selected during the design of the echo canceller, and T is the clock interval of the analog-to-digital converter (this is also characteristic of the prototype ) For example, C 6, XM assumes the following meanings: 0002, 0012. 0102, etc. (see; Fig. 2-a). This signal is fed through the switch 2 to the first address input of the memory unit 6, and then with the corresponding delay, determined by the first 11 memory register, to the other address inputs of the memory unit 6. As in the prototype, the control input of the key 14 from the control unit 13 at the time instants multiple of CT receives signals of duration T. As a result, at the indicated time instants, the code combination Ui 100 ... 02 appears at the input of the first 3 digital-to-analog converters 2, where r is the number of bits at the output of matching block 1. For example g 3, in this case Ui 10002 (see Fig. 2-6). The first digital-to-analog converter 3 converts the indicated code combinations into voltage pulses U (t), the shape of which at the input of the analog-to-digital converter 4 changes due to the influence of the input resistance

echo tract (see Fig. 2-g, dashed line). For the specified signal U (t) the following expression is true:

U (t) (t) -n (t-T), (1) where h (t) is the echo path response to a single

function.

When the U (t) signal is converted into binary form by an analog-to-digital converter 4, a quantization error occurs that can be represented

as a noise signal A (t) with dispersion G D / 12, where D is the quantization step of the analog-to-digital converter. In addition, there is interference Y (t) in the echo path, which can also be represented as a noise signal.

since the interference is not correlated with the signal

U (t). In FIG. 2 c shows a plot of samples A + YI. and in FIG. 2 g (solid line) - plot of a binary signal at the output of the analog-to-digital converter 4, which can be represented as a sum:

Ui + Ai + YI 2r {h (IT) - h (I - 1) + A. + YI. (2)

In FIG. 1 signal Ui + AI + YI goes to

the input of the multiplier 15, while the signal Xm is supplied to its other input (see, Fig. 2 a). As a result of multiplying these binary signals by one another, a binary combination is formed at the output of the multiplier:

Ui - Xm {2r {h (IT) - h (I - 1) + Ai + YI. (3)

In block 6 of the memory in the cells at addresses Xm

Wi Yi / 2r signals are recorded. Division

in 2G, it does not require the use of an additional device and is carried out by shifting to the right of the binary combination Ui by k binary bits. Thus, in the cell of the memory unit 6, the following signal samples are recorded at the addresses Xm (see Fig.

2 d):

Wi Xm h (iT) - h (i - 1) + Xm (A (+ YI) 2G. (4) From the analysis of expression (4) it follows:

1. A useful component of the signal samples recorded in the memory block, which is the first term of the right-hand side, is the convolution of the input signal Xm with the input resistance of the echo path connected to the output of the digital-to-analog converter 3 (the echo is typical for prototype), which proves the efficiency of the proposed echocompensator.

2. The error in the form of quantization noise and the interference at the moment of learning the communication channel, representing the second term of the right-hand side of expression (4), is reduced with respect to the prototype by multiplying the numerical value of the specified error by the factor Xm / 2g. moreover, this coefficient, as follows from the operation of the echo canceller, is less than 1 (for example, in our example, 2, then 10002.

After training, the echo canceller switches to the duplex information mode by the signal of the control unit 13. The operation in this mode of the device of the invention does not differ from the operation of the prototype.

Claims (2)

The claims An echo canceller containing a sequentially connected matching unit and a first switch, the second information input of which is connected to the output of the driver, code combinations, the input of which is connected to the output of the control pulse generator and to the control inputs of the matching unit, first and second memory register, control unit and analog-to-digital converter, the information input of which is connected to the output of the first digital-to-analog converter and is connected to the echo path, and the output is connected to the first input of the subtracter, 5 the first output of the control unit is connected to the control input of the first switch, the output of which is connected to the first address input of the memory unit and the input of the first memory register, the outputs which is connected to 2 ... N by the address inputs of the memory block, the information input of which is connected to the input of the second memory register, the outputs of which are connected to 1 ... (N - 1) information inputs of the memory block, 5 whose outputs are connected to the corresponding inputs of the adder, the output of which is connected to the second input of the subtractor, the output of which is connected to the input of the second digital-to-analog converter, the second and third outputs of the control unit are connected respectively to the control input of the memory unit and the control input of the key, the output of which connected to the input. house of the first digital-to-analog 5 a converter, characterized in that in order to increase the noise immunity to quantization noise of the analog-to-digital converter, as well as to interference present in the echo path at the time of training, 5, a multiplier and a second switch are introduced, the output of which is connected to the key input, and the control input is connected to the control input of the first switch, the output of which is connected to the first inputs of the second switch and multiplier, 0 the second input of which is connected to the outputs of the analog-to-digital converters; the output is connected to the input of the second memory register.