SU1001114A1 - Computing device - Google Patents

Description

(54) COMPUTATIONAL DEVICE

one

The invention relates to automation and computing, and is intended in particular for the functional conversion of digital signals to analog signals.

A computing device is known comprising a pulse generator, first and second counters, an analog-to-digital converter, a code comparison unit, a code-frequency representative, a decoder, a memory unit, an AND element, a reversible counter, a sign trigger, a register, an analogue duplicating unit, an output operational amplifier 1}

The disadvantage of this cleanup device is reduced performance when re-running various functions, due to the difficulty of reconfiguring a computing device when switching from one reproducible functional dependence to another. .

Closest to the proposed is a computing device, with "

the digital-analog multiplier unit connected by the output to the output of the operational amplifier by the analog input - to the analog signal input bus of the first multiplier, and the digital inputs to the outputs of the first register connected by information inputs to the outputs of the reversible counter, and input input with the output of the code comparison unit, the perv of the input group of which is connected to the output of the bits of the first and second counters, and the second input of the inputs to the outputs of the second register, coejEmeetraoro information moves to the input bus

ts of the argument code, and the control input from the start of its second counter and the control input of the third register connected by information inputs to the function code input bus, and the outputs to the inputs of the first decoder connected by outputs to the first group of address inputs of the memory block ti connected by the sign output to the sign trigger input, digital outputs to the first group of inputs of the first code-frequency converter, and the second group of address inputs to the outputs of the second decoder connected by inputs to the outputs the bits of the second counter connected to the output of the first bit of the first counter, the counting input of which is connected to the output of the pulse generator and to the first input of the first element, AND connected by the second input to the output of the first code-frequency converter, connected to the second a group of inputs with outputs. The dimensions of the first counter, with the output of the first element I connected to the counting input of the reversible counter connected by the control input of the reverse with the output of the trigger of the sign C2 The disadvantage of the known device is mc is a limited class of solvables, because it allows generating the output analog signal 2 in the form of multiplying the value of the analog factor v by the value of the function F (selected from some set of V functions) from the argument Ny, represented in the code: Z VFvlHx ) The purpose of the invention is to expand the class of tasks. The goal is achieved by the fact that a computing device containing a digital-analog duplicating unit connected to the input of the south operational amplifier, an analog input to the analog signal input signal of the multiplier, and digital inputs to the outputs of the first register connected by data inputs with the outputs of the reversible counter bits, the control input with the output of the code comparison unit, the first group of inputs of which is connected to the outputs of the bits of the first and second counters, and the second group of inputs ov - to the outputs of the second register connected by information inputs to the input bus of the argument code, and the control input to the output of the higher bit of the second counter and to the control input of the third register connected by information inputs to the input bus of the function code, and outputs to the inputs of the first do of an encoder connected to vod: a walker and with a pv {address address input group of the memory unit connected by a output to the sign trigger run, digital outputs to the first group of inputs of the first code-frequency converter, and a second group of address inputs to the outputs of the second decoder connected by inputs to the outputs of the bits of the second counter, connected by a counting input to the high-end output of the first counter, the counting input of which is connected to the output of the pulse generator and to the first input of the first element I, connected to a 1d input To the output of the first code-frequency converter, connected by the second group of inputs to the bits of the first counter, the fourth register, the second code-frequency converter, the third counter, the half-combinator and the second And element connected by the output to the counting input of the reversible counter, and the first input - with the output of the first element I and with the counting input of the third counter connected by the outputs of the bits to the first group of inputs of the second converter of the code-frequency connected by the output with the second input of the second element This And, and the second group of inputs - with the fourth register, connected by a control input to the high-order output of the second counter, informational inputs - to the input bus of the code of the second factor, and the sign bit output to the first input of the half-adder, connected by the second Input to the output the trigger of the sign, and the output with the control input of the reversible counter reversal. The drawing shows a block diagram of the numbering device. The device contains a pulse generator 1, the first element AND 2, the first and second counters 3 and 4, the first decoder 5, the memory block 6, the trigger 7 characters, the first code-frequency converter 8, the reversible counter 9, the first register 10, -digit analog duplicating unit 11, block 12 comparing codes, second and third registers 13 and 14, second deshi ({rator 15, output operational amplifier 16, second element 17, three & t counter 18, second code-frequency converter 19, fourth register 2 and a half-adder 21. Digital-analog duplicating 11 is connected to the output of the device The cell is 16, the analog input is to the input bus of the analog signal of the first multiplier, and the digital inputs to the outputs of register 10. The register U is connected by information inputs to the outputs of the bits of the reversible counter 9, and the control input is from the output of the code comparison unit 12, first the input group of which is connected to the outputs of the bits of counters 3 and 4, and the second group of inputs to the outputs of register 13. Register 13 is connected with information inputs to the input bar of the argument code, and the control input is connected to the output of the higher discharge of counter 4 and the manager the input of the register 14 connected by the information inputs to the input line of the function code, and the outputs to the inputs of the decoder 5. The decoder 5 is connected to the first group of address inputs of the memory block 6 connected by the sign output cm to the trigger input of the 7th character, digital outputs to the first group of converter inputs 8 code-frequency, and the second group of addresses: x inputs - to 1 inputs of the decoder 16. The inputs of the decoder 15 are connected to the outputs of the bits of the counter 4 connected by the counting input to the output of the higher bit of the counter 3 It is united with the output of the generator 1 and with the first input of the element I 2, connected by the second input to the output of the converter 8 code-frequency, the second group of inputs of which is connected to the outputs of the bits of counter 3. The element 17 is connected to the output with the counting input of the reversible counter 9, and the first input is from the output of the element I 2 and with the counting input of the counter 18 connected by the bit outputs to the first group of inputs of the 19-frequency converter. Converter 19 is connected by the output to the second input of the element And 17, and the second group of inputs to the outputs of the register 2O, connected by information inputs to the code input line of the second factor, the input control - to the output of the high digit of the counter 4, and outputs of the sign bit to the first input of the half adder 21. The secondary adder 21 is connected to the second input to the trigger output 7 of the character, and the output to the control input of the reversible counter reversal 9. The computing device operates as follows. Argument NX of the reproduced function in pythonic form enters the information inputs of register 13, from the outputs of the bits of which enters the second group of inputs of block 12 of code comparison. The selection function of the reproduced functional dependencies WL is numerically fed to the information inputs of register 14 and through the decoder 5 affects the first group of address inputs of memory block 6, thereby ensuring the choice of coordinate increments corresponding to the approximating function F required at the moment. {NX) from among P m - y. the number of bits of the code N.) approximating functions, the coordinate increments of which are recorded in block 6 of the memory). The rectangular pulses from the output of generator 1 are recalculated in series by the first 3 and second 4 counters. The fast counter 3 inserts into a piecewise linear approximation of each segment of a given function F (N), and the slow counter 4 serves to find the current values of the increments of ordinates of the approximation nodes of this function through the decoder 15 in block 6 of the memory. The signals from the outputs of the bits of the counter 3 and the counter 4 are fed to the first group of inputs of the code comparison unit 12. When the codes at the output of the register 13 and in the counters 3 and 4 at the output of the code comparison unit 12 are equal, a signal is generated that arrives at the control input of the register 10 and allows the code from the output of the reversible counter 9 to be written to it. Converter 8 code-frequency, correct for the second group of inputs, for the outputs of the bits of the counter 3, and for the first group of inputs, for the outputs of memory block 6, form; At the output, the account resolution signal, which is fed to the input of the element AND 2 and permits the passage of rectangular tpuls from generator 1 to the counting input of the third counter 18 and the second element AND 17, depending on the increments of the neighboring ordinates of the approximation nodes of the given function. The second code-frequency converter 19, controlled by the first group of inputs, the bits of the counter 18, and (That is, the second group of inputs - the outputs of the register 2O, 11It output the signal, the account resolution, which enters the input element And 17 and. .direction of rectangular pulses from the output of the element I 2 to the counting input of the reversing counter 9, depending on the code value of the second cross-multiplier M, arriving at the cc (| juicer inputs perRcispa 20. The half-adder 21 produces two modulo two signals from the sign bit and register 20 and trigger output 7, and controls the reverse of the reversible counter 9. The outputs of the bits of the reversible counter 9 control the keys of the digital 710 analog multiplying unit 11 through the register 10. The analog input of the block 11 is the input of the analog signal of the first multiplier W. The code-frequency converter 8 ensures the obtaining of a given slope of each section of the approximating funkta and operates in accordance with the logical expression: UV v V v24p4f, ... v 2 -1: .. where H is the code at the outputs of the bits of counter 3; - code on digital outputs V. - V. memory block; -output signal of the converter 8 code-often Converter 19 code-frequency works in a similar way and in conjunction with counter 18 and element 17 provides for the transmission of pulses from the output of element 2 to the counting input of the reversible counter 9 with the transfer coefficient of the digital multiplier M recorded in register 20. The high-order output of counter 4 is connected to the control inputs of input 13, third 14 and fourth 20 registers. Due to this, at the moments of time corresponding to the overflow of counter 4, the digital argument NX, the digital control signal N and the digital factor M. are overwritten. Generator 1, first 3 and second 4 counters, decider 15, memory block 6, converter 8 code -frequency, element 2, trigger 7 characters, counter 18, converter 19, register 20, element 17, half adder 21, reversible x interlacer 9 perform a time scan of a piecewise linear approximation function with its simultaneous multiplication by a digital multiplier M according to his mark. Using block 12, code comparison and register 1O, the moments of the ordinates of the temporal and given functions for the digital argument NX written to register 13 are fixed. In this case, the code of the current ordinate of function T (NX) corresponding to the input argument NX of the control code iia factor M, enters the digital inputs

Claims (2)

1. USSR author's certificate number 783804, cl. Q About Q 7/12, 1979. 2. USSR author's certificate in application number 29O4372 / 18-24, fui. C, O6U D / OO, G 06 Q 7/26, 198O (prototype). Hh Hi