SU1300542A1 - Device for displaying information on cathode-ray tube screen - Google Patents

Abstract

The invention relates to the field of computer technology and is intended to construct devices for displaying graphic and symbolic information on a CRT screen. The purpose of the invention is to increase speed - by introducing a comparison unit 4, registers 5,7,17 and 18, switches 6 and 20, an element of OR 13, a block 19 of permanent memory, keys 22 and 27 with corresponding connections. The speed increases (lO% with a uniform distribution of vectors over the tilt angle) due to the construction of vectors with close projections with a speed greater than the nominal one, but the construction speed of each of the projections does not exceed the nominal one and the coordinate amplifiers of the indicator are not overloaded. 1 il. o (l so about o ate j y

Description

The invention relates to computing and is intended to construct devices for displaying graphical and symbolic information on a CRT screen.

The purpose of the invention is to increase the speed of the device.

The drawing shows the functional diagram of the device.

The device contains the first shift unit 1, whose information inputs are the first 2 and second 3 device inputs, comparison unit 4, first register 5, first switch 6, second register 7, decoder 8, first key 9, clock generator 10, divider 11 frequencies, first counter 12, element 13 OR, second 14 and third 15 counter, second shift block 16, third 17 and fourth 18 registers, permanent memory block 19, second switch 20, third digital-to-analog converter 21, second key 22 , multiplier 23, first adder 24, CRT 25, fourth digit analog converter 26, the third key 27, the multiplier 28, the second adder 29, the first 30 and the second 31 digital-to-analog converters (DAC).

Positions 32-36 designate the third through seventh inputs of the device.

The device works as follows;

When displaying vector information codes of the coordinates of the beginning of the vector are received at the inputs 32, 33 on the DAC 30 and 31, respectively. The output signals from the DAC 30 and multiplier 23 and DAC 31 and multiplier 28 are summed by adders 24 and 29 respectively - the CRT beam is set to the starting point of the vector. The multipliers 23 and 28 multiply the digital-analog multiplication of the digital argument — the codes of the magnitudes of the vector projections on the axes — on the analog time function (reference signal), which determines the nature (time and speed) of the beam moving along each of the coordinates. A sawtooth-shaped reference signal is generated by the DACs 21 and 26 in accordance with the codes arriving at their input. The keys 22 and 27 are set in accordance with the information received at the input 36, the sign of the reference signal for each of the coordinates, thereby determining the direction of movement of the beam. To ensure blue

Chronality of the construction of projections when displaying vector information on the inputs of the DAC 21 and 26 receive the same codes.

The high performance of the device is provided by controlling the time of vector construction depending on its size. The value of the larger of the vector projections is used as a regulating parameter, since when building vectors in the rectangular coordinate system, their calculation is associated with large time and hardware costs. The speed of the beam thus depends on the ratio of the magnitudes of the projections of the vector on the coordinate axes

2 2 1/2

V (R, + RJ /(K.MaksK ,, R.)),

one)

where V is the speed of the beam; Rj (, RN values of the projections of the vector on the corresponding coordinate about si;

K - scale regulation factor. Otherwise

t2

V (1+ (min (K R) / MaKc (R ,, R,)))

(2)

From (1) and (2) it follows that the speed is maximal with equal projections (, 1 / К 4Т) and minimal with equal smaller projection zero

()

The nominal speed Vn is set to

V.

 min

This allows to increase the speed of the device (about 10% with a uniform distribution of vectors over the angle of inclination) due to the construction of vectors with close projections with a speed higher than the nominal one (however, the construction speed of each of the graphs does not exceed the nominal not overwhelmed).

The comparison of the values of the projections arriving at the inputs 2 and 3 is carried out by the comparison unit 4 (the shift of the projection codes in the shift unit 1 is turned off by the gating of the shift control decoder 8). The result of the comparison is stored in register 5 and is used to control the switch

313

, 6 in such a way that, at its output, a larger projection code is transmitted, which is stored in register 7 and is subsequently used as a code regulating the time of vector construction. The signals controlling the recording of information in registers 5 and 7 and gating of the decoder 8 arrive at the control inputs of the registers and the second input of the decoder 8 at input 35. Reducing the building time with decreasing control code leads to an increase in the steepness of the sawtooth reference signal (since its amplitude remains constant to provide a given amount of movement of the beam on the screen of a CRT 25) to values at which the multiplication error becomes unacceptably large. Limiting the increase in steepness allows a stepwise decrease in the amplitude of the reference signal while decreasing the magnitude of the control code. In order for the amplitude of the output signals of the multipliers to remain corresponding to a given beam movement, the vector projection codes on the digital inputs of the multipliers 23 and 28, respectively, are increased. The increase in the projection code is realized in the most simple way by shifting m bits in the direction of the older ones with decreasing the control code 2 times in relation to the maximum, where m is a positive integer other than zero. Accordingly, the amplitude of the reference signal is reduced by a factor of 2. The shift is implemented in block 1 by the control signals generated by the decoder 8 based on the analysis

the number of insignificant bits n in the regulatory code

P.

 p - n

 o h where n is the width of the project code

and regulatory code; n is the number of significant bits of the regulatory code. The range of change in the slope of the reference signal is determined by the discreteness of the change in the magnitude of the shift implemented by register 1. Let

m m.

shift value in block 1} discreteness of change of shift value (the minimum realizable shift);

с - a natural number - the multiplicity of the shift.

Then the amplitude of the reference signal and the magnitude of the projection shift in block 1 are the same for vectors, the control codes of which vary from

L,

 2

2-1

nnio (

min

and the steepness of the reference with in

signal

Max/

min

 2

Wo

time,

Those. FOR: ensuring the ratio

K K

P

where Ki is the maximum allowable value for increasing the steepness, Sho

In the device, the closest regulatory codes are grouped together and the corresponding vectors are built at the same time. The sizes of the groups are chosen such that the relative change in the rate of construction in the group does not exceed a certain value.

SV SV,

(3)

The relative change in velocity in a group is determined by the formula

SV, - uV, - / V

n

where uV is the absolute change in speed in the i-th group. Because

LU- uL, - / t-, where t- is the time of building vectors, the regulatory code of which is included in the i-th group; uL; - the absolute change in the value of the regulatory code in the i-th group (group size),

0

then SV

 & Lj / lh; V.

(four)

ti

five

where b „.

From (4) it follows that in order to fulfill (3) the size of the group should decrease with decreasing. In the proposed device, the division into groups, the size of which is halved with a decrease in the control code, is realized. For this, only the eldest of n, the significant bits of the control code, are used to adjust the duration. The size of the group is determined by the number of bits unused to control.

& L:

n,; - e

(five)

the number of significant bits of the control codes of the i-th group, from uL.

(with n; 1).

mks

2

"four

BEFORE

The number of groups of the same time, e (6)

measure P 2

From (4) and (5) it follows that

SV; 2

Enough to accomplish (3)

2 sv,

which determines the minimum number of most significant bits of the control code used to control

d - logjsv

25 step-increasing function, interpolating the sawtooth reference signal with a constant amplitude step. The second step-increasing function, formed by block 19, interpolates the reference signal between the interpolation points of the first function. A 2 times decrease in the amplitude of the reference signal and the build time during the shift

and the maximum relative velocity change in a group when using a certain number of bits

° -SV with 2 Sampling t of the most significant bits from the regulating code, carried out by successively connected blocks 1 and 16 of the shift in accordance with block 1 of the vector projection codes on the control signals, which are generated by reducing the decoder, cue the number of reads block pages

19 by turning off the high-order m bits of the counter 14 with a key 9, 40 that blocks the generation of clock pulses by the generator 10,

If the value of m is greater than the number of bits of the counter 14, the key turns off the counter 14, and the necessary time will be needed (t, 0) and it can be 5 vector structures given by the divisor

11 frequencies. The pages of block 19 used in this case, the transition to which is determined by the decoder 8, are read only once (first

Block 1 shifts by

m hectare

bits, and 16 - on the remaining

m, Po - i Goo

bits, t, e, when in block 16

be excluded from the scheme.

The number of values of the steepness of the sawtooth reference signal, implemented by the device, is determined by the number of gru; np control codes (the 0 interpolation function is zero), which corresponds to the amplitude, therefore the amplitude of the reference signal is necessary. When the selected "O Q signal is determined by the value

the method of adjusting the size of the group and the amplitude of the reference signal with the reference signal of the same amplitude is constructed in vectors of groups of sizes. Then,

last on the code page.

taking into account (6), the number of realizable steepness values is determined by the formula N

nioP

m ,, 2

e-1

Since the step of variation in amplitude of the first step-increasing function is constant, and the number of codes recorded on the page is proportional to the value of the 2-digit code.

The same number of arrays (pages) needed to form the reference signal has a block of permanent memory. Page number used

it is determined by the E-bit code obtained by shifting the control code in blocks 1 and 16 (this gives 2 combinations, since the most significant bit of this code is significant, i.e.

nonzero) and the number of significant bits in the code shifted by block 1 of the larger vector projection (which can take values from 0 to). Block 19 is forming

only the low bits of the reference signal code. The higher bits are generated by a counter 14, which counts the number of reads of a given page of block 19, that is, e, which accumulates. The generated code is fed to the inputs of the DAC 21 and 26 through registers 17 and 18, respectively.

Thus, using the counter 14, a first step-increasing function is formed, interpolating the sawtooth reference signal with a constant amplitude step. The second step-increasing function, formed by block 19, interpolates the reference sign between the interpolation points of the first function. A 2 times decrease in the amplitude of the reference signal and the build time during the shift

 block 1 of codes of projections of the vector into bits is performed by decreasing the number of reads of the block pages

last on the code page.

Since the step of variation in amplitude of the first step-increasing function is constant, and the number of codes recorded on the page is proportional to the value of the 2-digit code.

(to provide the necessary time to build a vector), the step in amplitude of the second step-increasing function also depends on the value of the E-digit code, i.e. on each page of block 19 the codes of the reference signal of a certain slope are recorded. The sequential reading of codes recorded on a given page is provided by counter 12. Resetting counter 12 at the end of the page (returning to the top of the page) is done by frequency divider 1, the division factor of which is set depending on the value of the H-bit code and matches with the number of words on the block 19 page used.

The initial state of the counters 12 and 14 determines the code arriving at input 34 (when displaying vector information, this code is zero). The signal controlling the recording of the zero code in the counters also enters input 34. Counter 15 is not used in the construction of vectors.

When displaying symbolic information, the coordinates codes of familiarity go through the inputs 32 and 33 to the DACs 30 and 31, respectively, setting the beam of the CRT 25 to the lower left corner of the familiarity. At the inputs of multipliers 23 and 28 to inputs 2 and 3, respectively, the output word of block 19 contains two service bits. The first of them is used to prohibit the generation of clock pulses by the generator 10 upon completion of reading from the display mark description block 19; the value prohibiting the generation of pulses is only in the last layer of the description of each character. The second service bit controls the presence of illumination of the symbol end point, described by the currently read word of block 19. Its value is determined when composing the contour description, specifically the code that determines the size of the sub-character to display. Decryphra 35 sign. The second service source 8 is gated with a signal, the incoming has to do with the generator at its input from input 35, so that the prohibition is disabled. generating clock pulses from the key 9 and squel r in block 1. 40 The output signals of the DAC 30 and multiplier 23 and DAC 31 and multiplier 28 are summed by adders 24 and 29, respectively.

A positive-tube (CRT), containing the first block, is fed to the input of the reference voltage of 45 on the screen of the electron-beam inhabitants 23 and 24

coordinate deviation signals, and is used to modulate the beam brightness and therefore not shown in the diagram.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION A dp display device is information (in accordance with the information set when displaying characters on the input bus 36) output signals of the D / A converters 21 and 26, respectively, which allow the beam to move along the contour of the displayed character. The required DAC input code 21 and 26 is read from block 19 in accordance with the state of counters 12, 14 and 15. Registers 17 and 18 reduce the duration of the transition process at the inputs of DAC 21 and 26. Respectively. The beginning The current state of the counter (the address of the beginning of the array, its description of the displayed character, in block 19) determines the code arriving at the input 34. The frequency divider 11 is turned off by a signal coming from input 35 to its control input, therefore, a change in the state of counter 14 is caused only by overflow of counter 12. A signal arriving at the input 35, p. using the switch 20 also sets the state to logical. О in the generated by the display of vectors by the counter 14 and unused when displaying the symbolic information, since the size of the symbol is significantly smaller than the screen size, the higher bits of the input code of the DACs 21 and 26. The output word of block 19 contains two service bits. The first of them is used to prohibit the generation of clock pulses by the generator 10 upon completion of reading from the display mark description block 19; the value prohibiting the generation of pulses is only in the last layer of the description of each character. The second service bit controls the presence of the illumination of the symbol contour point, described by the currently read word of block 19. Its value is determined when composing a description of the contour of a particular sign. The second service bit is not related to the formation coordinate deviation signals, and is used to modulate the beam brightness and therefore not shown in the diagram. The invention of the device dp display information shift, the information inputs of which are the first and second inputs of the device, the control input is connected to the output of the decoder connected to the control input of the second shift unit and the first control input of the first key, the output of which is connected to the first control input of the clock pulse generator , the output of which is connected to the counting inputs of the frequency divider jH of the first counter, the reset input of which and the second control input of the first key are connected to the output of the frequency divider, the information input of the first switch key With the output of the second counter, four digital-to-analog converters, the information inputs of the first and second digital-analog converters are the third and fourth inputs of the device, their outputs are connected to the first information inputs of the first and second adders, respectively, the second information inputs of which are connected to the outputs of multipliers The information inputs of which are connected to the outputs of the first shift unit, the outputs of the adders are connected to the deflection system of the CRT, the information inputs of the first and second The counters are the fifth input of the device, characterized in that, in order to increase the speed of the device, it contains a comparison unit, the inputs of which are connected to the outputs of the first shift block, four registers, two switches, the OR element, the second and third keys , the third counter, the counting input of which is connected to the overflow output of the second counter, and the information input is connected to the fifth input of the device, the counting input of the second counter is connected to the output of the OR element, the 9THERS of which are connected respectively to the output of the overflow and the second counter and the output of the divider, and a unit nonvolatile memory, data inputs of the first switch connected to the first shift block outputs, a control input - with the output of the first register information Editor H, Gorvat Compiled by And, Zaginayko Tehred A. Kravchuk Proofreader T, Kolb Order 1155/51 Circulation 434Subscription All-Union Scientific Research Institute of the USSR State Committee for inventions and discoveries 113035, Moekva, Zh-35, Raushsk nab. d. 4 / .5 Production and printing company, Uzhgorod, st. Project, 4 the input of which is connected to the output of the comparison unit, the output of the first switch is connected to the information inputs of the second shift unit, the second the register and frequency divider controlling the inputs of the first and second registers, the decoder, the frequency divider and the second switch are the sixth device input, the information input of the second switch is connected to the second counter output, and its output is connected to the first information inputs of the third and fourth registers informational inputs of which are connected to the first and second outputs of the permanent memory unit, and the control inputs are connected to the output of the clock generator, the outputs of the third and fourth register are respectively connected to the inputs of the third and fourth digital to analog converters, the outputs of which are connected to the data inputs of respectively the second and third keys yushie control inputs of which are the seventh input of the device, and their outputs connected to inputs of reference voltages of the first and second multipliers, the third the output of the fixed memory unit is connected to the second control input of the generator of takt pulses, the output of the second register is connected to the information input of the decoder, the output which is connected to the first control input of the storage unit, the address inputs of which are connected to the outputs of the first, second and third counters, the second control the 1st input block. memory is connected to the output of the second block shift.