SU1513506A2 - Device for displaying information on crt screen - Google Patents

Abstract

The invention relates to computing, is intended to display graphic and symbolic information on a CRT screen and can be used as a peripheral computer device. PURPOSE OF THE INVENTION IS THE EXPANSION OF THE FIELD OF APPLICATION OF THE DEVICE THROUGH THE POSSIBILITY OF IMPLEMENTING THE ARC DISPLAY. THIS IS ACHIEVED BY THE INTRODUCTION OF THE SECOND UNIT 45 OF A CONSTANT MEMORY, THE SQUARE PERSONAL DEVIATOR 20 OF THE FREQUENCY, THE THIRD 17 AND THE FOURTH OF THE CURRENT DEVICES OF THE 18 CODES, THE TRANSFORMERS OF THE 18 CODES, THE SWITCHERS 22,29,35,36,36, 14 HIGH PRODUCTIVITY OF THE DEVICE WHEN BUILDING ARC CIRCUITS IS PROVIDED BY REGULATING THE TIME OF ARC BUILDING DEPENDING ON ITS RADIUS. TIME REGULATION IS IMPLEMENTED UNDER THE BINARY LAW: REDIUS REDUCTION DOUBLES THE CONSTRUCTION TIME DECREASED BY DOUBLE BY ANY LENGTH OF THE ARC LENGTH CODE. SIMPLE, DEFINITIONS 1 IL.

Description

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3 1513506 exploring the field of application of the device with the capability of providing the display of neighborhood arcs. This is achieved by introducing the second memory block 45, the second frequency divider 20, the third 17 and fourth 19 shift blocks, the 18 LODS converter, the switches 22, 29, 35, 36 and 42 and the corresponding functional connections. High performance of the device when constructing arcs of circles is provided by controlling the time of arc construction depending on

from its radius. The time regulation is carried out according to the binary law: with a decrease in the radius, the building time is halved by the block 19 by the arc length code code. At the same time as the arc length code is halved, the transition to the use of other arrays of the block 45, which are half the values of the sine moduli and cosine on the same range of angles from O to / G to provide for the construction of an arc of a given angular value, 1 tabl, i il.

The invention relates to computing, is intended to display graphic and symbolic information on the screen of a CRT, can be used as a peripheral computer device and is an improvement of the device according to AV (r. K 1300542,

The purpose of the invention is to expand the field of application of the device by displaying arcs of circles.

The drawing shows the functional diagram of the device.

The device contains a shift unit 1 whose inputs are the first 2 and second 3 information inputs of the device, comparison unit 4, first register 5, first switch 6, second register 7, decoder 8. first key 9, clock generator 10 the first frequency divider 11 is the first counter 12, the element OR 13, the second 14 I the third. 15 counters, the second 16 and third 17 shift blocks, the code converter 18, the fourth shift block 19, the second frequency divider 20, and the information input of the block 19 is the seventh information entry 21 of the device.

. The device also contains a fifth switch 22, a third register 23, a third digital-to-analog converter (CDL) 24, a second key 25, a first C M southerner 26, a first adder 27, an indicator 28, a sixth switch 29, a fourth register 30, a fourth DAC 31, the third key 32, the second multiplier 33, the second adder 34, the third 35, the fourth 36 and the seventh 37 commutators. In addition, the device also contains the first 38 and second 39 PAP,

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the inputs of which are the third 40 and quarter 41 information inputs of the device, the second switch 42, the control input of which is the control input 43 of the device, and the first 44 and second 45 blocks of permanent memory, the Second information input of the switch 37 is the sixth information the device input 46, and the information input of the frequency divider 20 is the fifth information input 47 of the device.

The device works as follows.

When displaying vectors. Codes of coordinates of the beginning of the vector are fed to the inputs 40 and 41 to the DAC 38 and 39, respectively. The output signals of the DAC 38 and multiplier 26 and PAP 39 and multiplier 33 are summed by adders 27 and 34, respectively - the beam of the indicator 28 is set to the starting point of the vector. The multipliers 26 and 33 multiply the codes of the projections of the vector on the coordinate axes by the reference signals, which determine the nature of the movement of the beam, for each of the coordinates. The polarity of the reference signals of multipliers 26 and 33 is set by the second 25 and third 32 keys, respectively, according to the signals received at their control inputs through the switch 37 from input 46. The input signals of the keys j 25 and 32 are formed by the DAC 24 and 31, respectively. To ensure the synchronization of the projection, the same codes are received from the DAC 24 and 31 inputs from registers 23 and 30, respectively. Older code bits are generated by counter 14 and fed to the inputs of registers 23 and 30 from the output

switch 42 through switches 22 and 29, respectively. and the lower bits of the codes are in block 44 (the same on the second and first outputs) and the inputs 35 and 36, respectively, arrive at the inputs of registers 23 and 30 through switches. Switches 22, 29, 35-37, and 42 are set to a required state by signals arriving at their control inputs on input 43.

High performance of the device is provided by regulating the time of vector construction depending on the magnitude of its larger projection. The larger projection is sampled by the switch 6 in accordance with the signal arriving at its control input through the register 5 from the output of the comparator unit 4. The larger projection code is stored in register 7 and is used by decoder 8 as a time-regulating constructor. The shift of the projection codes, coming in on inputs 2 and 3, in block 1 of switches by gating the output of the decoder 8 by the time of forming the regulating code. The signals controlling the gating of the decoder 8 and the recording of information in registers 5 and blunt on the input 43.

The increase in the steepness of the reference signals to unacceptable sizes is limited by a stepwise decrease in a number of reference signals by 2 (t is a natural number) times. The codes of the vector projections are shifted by m bits towards the higher ones so that the amplitude of the output signals of the multipliers remains corresponding to the specified

Shifting The shift is carried out by block 1 in accordance with the control. based on the analysis of the number of insignificant bits in the time regulating code.

To regulate the time, it will not use only the n most significant bits of the regulating code, which corresponds to dividing the regulating codes into groups, the size of which will be halved as the regulatory code will be halved. The vectors, the control codes of which belong to the same group, are built at the same time, which makes it possible to reduce the number of values of the steepness-reference signal realized by the device, equal to the number of the control groups, after

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codes that correspond to the same lp-pituit of the reference signal (adjustable also depending on the size of the control code).

Block 44 contains as many arrays (pages) as steepness values are implemented by the device. On each page of block 44, linearly increasing codes of the reference signal of a specific slope are recorded. The codes written on the page using this value of the regulating code are sequentially read by the counter 12. It is reset to zero at the end of the page (return to the top of the page) by a frequency divider 11, whose division scale corresponds to the number of words on the given page and is determined by the higher bits of the larger projection code shifted by block 1, the Output signal of the frequency divider 11 also initiates a transition to the next. state of the counter 14, i.e. the latter counts the number of reads of the used page of block 44 (accumulation),

Thus, the device interpolates the linear (sawtooth) reference signal with a step function. The latter is the sum of two fz functions, one of which is formed by the counter 14 and therefore performs interpolation with a constant amplitude step. The second of these is formed by block 44, and is interpolated by the melody by the interpolation points of the first function. The number of interpolation points of the second function is equal to the number of words on the used page of block 44, which provides the necessary slope of the reference signal and the time to build the vector.

The reduction of the reference signal by a factor of 2 and the time of building the vector when shifting the projection codes in block 1 by m bits is reduced by decreasing the number of reads of the used page of block 44 by 2 times by turning off m high bits of the counter 14 using the first key 9, which prohibits the generation of clock pulses of the GTI 10 at a certain (decrypter depending on the number of insignificant bits in the control code) state of state 14.

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The frequency converter 20 when displaying symbols and vectors is turned off by a signal received at its control course on input 43, and therefore does not affect the operation of the GTI 10. If the value t is greater than the number of bits of the counter 14, the key 9 completely disables the gray one, to prohibit the generation of pulses, the output signal of frequency divider 11. The pages of block 44 used for this, the transition to which is determined by the decoder 8, are read once

The initial state of the counters 12 and 14 determines the code arriving at input 21 (this code is zero when displaying vector information). Counter 15 is not used when building vectors. The signal controlling the recording of the initial state in the counters is input 47,

When displaying symbolic information, the codes of the familiarity coordinates are received at inputs 40 and 41 on the Digital Indicators 38 and 39, respectively. The output signals of the CLP 38 and multiplier 26 and IDP 39 and multiplier 33 are summed by adders 27 and 34, respectively - the beam of indicator 28 is set in the lower left corner of the familiarity. The code inputs of multipliers 26 and 33, through inputs 2 and 3, respectively, receive a code that determines the size of the displayed symbol (the shift in blocks 1 and 19 is pre-disabled by gating the output signal of the decoder for the entire time the symbol is formed by the signal arriving at the input of the decoder 8 at the entrance 43).

Pa the input signal of the multipliers 26 and 33 receive positive (in accordance with the information received when the-1 symbols are displayed via the sytatop 37 code from input 46 to the control inputs of keys 25 and 32) the output signals of the digital signals 24 and 31, respectively, providing the movement of the beam along the contour of the displayed ciiMBO-la. The low bits of the input codes of the DAC 24 and 31 go to them from the first to the second outputs of block 44 through switches 35 and 36 and registers 23 and 30, respectively, and the high bits from the input of switch 42 through closures 22 and 29 and registers 23 and 30 respectively. The switch 42 provides, when mapping. Symbols, the zero state generated by

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the mapping of the vectors by the counter 14 high-order bits of the input codes of the DAC 24 and 31. The required state of the switches 22, 29,35-37 and 42 is set by the signals received on their control by the inputs 43.

The initial state of the address counter of the block 44 formed by the serially connected counters 12, 14 and 15 determines the code arriving at input 21 through block 19 (the shift in block 19 is turned off, as indicated).

The signal, controlled by writing the code to the counters, arrives at input 47.

The output word of block 44 contains two service bits. The first of them is used to prohibit the generation of clock pulses by the generator 10 after the completion of the match from block 44 describing the displayed symbol: the value prohibiting the generation of pulses has only the last word description of each symbol in the second word. The second bit controls the galaxy illumination of the character outline point S The described readout is currently the word of the block 44. Its value is determined when composing the outline of a specific symbol. (The second slot bit is irrelevant to the formation of a deviation of d15x signals and therefore is not shown in the diagram).

The dividers 11 and 20 of frequency when displaying cue of the wheels do not affect the operation of the device because they are turned off by the signals coming to their control inputs on input 43.

When displaying circular arcs, the codes of the coordinates of the center of the circle on which the displayed arc lies, on inputs 40 and 41, arrive at the DAC 38 and 39, respectively. The output signals of the PDP 38 and the clever .26 and PUSH 39 -and the multiplier 33 are summed with sum-iaTOrs 27 and 34, respectively, the indicator beam is set to the center of the circle, since at the initial moment the output signals of the multipliers are zero. During the construction of the arc of a circle, the multipliers perform digital-analog multiplication of the arc radius code by quadrature reference signals.

Codes of the reference signals are generated by block 45 containing the values of the modules of the sine and cosine angles from 0 to Y /. Sequential reading of codes from

block is provided with an address counter formed by serially connected counters 12, 14 and 15. The frequency divider 11 is turned off by a signal arriving at its control input on input 43, therefore the change in the state of counter 14 occurs only after counter overflow 12, Output codes of block 45 (cosine value and sine) are fed through switches 35 and 36 (low-order bits) and 22 and 29 (high-order bits) to the information inputs of registers 23 and 30, respectively. Registers 23 and 30 are designed to reduce the duration of transients at the inputs of DACs 24 and 31, which form unipolar reference signals, respectively. The polarity of the reference signals is controlled by the keys 25 and 32 in accordance with the information supplied to their control inputs converter 18 codes through switch 37. Switches 22, 29 and 35-37 are set to the required state by signals arriving at their control inputs on input 43.

The high performance of the device when constructing arcs of circles is ensured by regulating the time of construction of the arc depending on its radius. The time is controlled according to the binary law: with the radius reduced by half, the building time is halved by the block 19 of the arc length code input through input 21 to the information input of the frequency divider 20, to the right (in the direction of the minor bits). The magnitude of the shift determines with the decoder 8 on the basis of an analysis of the number of insignificant bits in the radius code received at its input from register 7. The input code of register 7 is generated by switch 6, and the state of the latter is indifferent, since when building arcs of circles along inputs 2 and 3, the inputs of block 1 (the shift in which is previously disabled by gating the output signal of the decoder 8 at the time of writing the code in register 7) receives the same arc radius code.

Frequency divider 20 generates a time interval proportional to the code received at its information input, during which the C-axis counter is changed.

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12, 14 and 15 n movement of the beam on the indicator screen, since its output signal prohibits the generation of tactical pulses of the GTI 10. Simultaneously with the reduction of the arc length code (block 19), the transition to the use of other arrays of block 45 containing half the values modules of sine and cosine on the same interval with an angle from O to n, so as to ensure the construction of an arc of a given angular value. In this connection, the code for the start of the arc, inputted at input 21, is written to the right in block 19 by the same value, before writing to counters 12 (low bits), 14 (middle bits) and 15 (high bits). as is the arc length code. The current quadrant number code in this case is contained in the adjacent two bits of the address counter, the position of which depends on the amount of shift in the block.

5 19. The allocation of the address counter bits containing the current quadrant number code is performed using block 17, shifting by the same amount as block 19, but in the opposite direction (left): the quadrant number code appears to be in the two higher bits of the output code of block 17, which are used to control the polarity of the reference signals of the multipliers. The code converter 18 is designed to generate from the code the quadrant number of the signals controlling the keys 25 and 32, similar to those arriving in the vector mapping mode at input 46. Its operation is illustrated by a table .. The signal controlling the writing of the code to the counters is fed through input 47 .

In order that, with a decrease in construction time, the steepness of the generated reference signals does not increase to values at which

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the resolution of the umolnsen becomes unacceptably large, with a decrease of 2

Once the arc radius code is used, a transition is made to the use of the arrays of block 45 containing the codes of the reference signals having the same amplitude. The arc radius code arriving at inputs 2 and 3 is, in this case, being shifted in block 1 by m bits to the upper (left) side, so that the amplitude in the next signals

multipliers remain the radius of the building arc corresponding to the radius. Shift and transition control to other arrays of block 45 is performed by decoder 8 based on an analysis of the number of insignificant bits in the radius code.

Claims (1)

Invention Formula A device for displaying information on the screen of a cathode ray tube according to avt.S. No. 1300542, characterized in that, in order to expand the application area of the device by displaying circular arcs, it contains a second fixed memory block, a second frequency divider, a third and fourth shift blocks, a control input of the third shift block, connected to the output of the decoder, and information inputs - respectively with the outputs of the first, second and third counters, the code converter, whose input is connected to the output of the third shift block, the third, fourth, fifth, sixth and seventh switches, the first information iibiii in the turn of the seventh switch is connected to the input of the code converter, the output of the second frequency divider is connected to the third control input of the clock, the output of the seventh switch is connected to control the inputs of the second and third switches, the inputs of the third and fifth switches are connected to the information inputs of the third register , the outputs of the fourth and sixth switches are connected to infor 061 mation inputs of the fourth register, control inputs from the third to seventh switches are connected to the control input of the device, the first information inputs of the fifth and sixth switches are connected to the output of the second switch, the first information inputs of the third and fourth switches are connected respectively to the second and third outputs the first block of permanent memory, the first output of the second block of permanent memory is connected to the second information inputs of the third and fifth switches, the second output of the second block The fixed memory is connected to the second information inputs of the fourth and sixth switches, the second information input of the seventh switch is the sixth information-OP1SH1M input of the device, the information input of the second frequency divider is connected to the fifth information input of the device, and the control and counting inputs of it are connected respectively, with the control and counting inputs of the first frequency divider, the control input of the fourth offset unit is connected to the output of the decoder, and the information input is the seventh information The device's input, the fourth shift output is connected to the information inputs of the first, second and third counters and the second frequency divider, the control input of the second fixed memory unit is connected to the decoder output, and the address inputs are connected to the first, second, and third counters, respectively.