SU1211756A1 - Function generator - Google Patents

Abstract

The invention relates to the field of automation and computing, in particular, to devices for piece-linear approximation of functions, and can be used as part of analog-digital computing systems. The converter contains the case of the argument argument block. pulse generator, reversible result counter, adder-subtractor of ordinates, dividing unit, delay element, reversible address counter, adder-subtractor of the abscissa, memory block of nodal values of the abscissa and ordinate, reversible counter of the argument, control unit of the counters, three pulse generators, two adders modulo two, four triggers, two elements AND, two elements OR, and two decoder zero. The meter control block consists of an AND element, an RS flip-flop, three NOT elements and two N-NLI elements. The functional converter extends the functionality by transforming the alternating functions in all four quadrants. 3 il. Ate 1 SL Od

Description

The invention relates to automation and computing, in particular to devices for piecewise linear approximations of functions, and can be used as part of analog-digital computing systems.

The aim of the invention is to enhance the functionality by converting alternating functions in all four quadrants.

Figure 1 presents the block diagram of the functional Converter; Fig. 2 is a functional diagram of a meter control unit; FIG. 3 shows several sections of the function approximation with different signs of the argument and ordinates. I

Functional converter

contains the argument register 1, the information input 2 of the converter, the argument subtraction unit 3, the generator of 4 pulses, the first element AND 5, the first controlled frequency divider 6, the reversible counter 7 of the result, the adder-subtractor 8 ordinates, containing the output of 9 characters and the output 10. nulls, block 11 divisions, element 12 delays, input 13 digits of the polarity of the argument, reversible counter 14. addresses, output 15 of the code of the adder-reader 8 ordinates, adder-subtractor 16 abscissa, blocks 17 and 18 of the nodal memory values of abscissas and ordinates respectively, reversible argument counter 19, output 20 digits of the difference block of the 3 subtraction of the argument, second controlled frequency divider 21, output of the zero subroutine of the argument subunit 3, the first element OR 23, the first decoder 24 zero, the second trigger 25, the first modulo 26, two, second decoder 27 zero, fourth trigger 28, second adder 29 modulo two counter control unit 30, first pulse shaper 31, third AND 32 element, second pulse shaper 33, second AND 34 element, second OR 35 element, third trigger 36 , exit 37 fourth trigger 28 , output 38 of the second adder 29 modulo two, the first trigger 39, the first 40 and the second 41 outputs of the block 30, the third driver 42 pulses and the third element OR 43.

The meter control unit 30 contains a third element I-SHSh 44,

562

N-trigger 45, in the second, the first and third elements are NOT 46-48, the first and second elements are AND-OR 49 and 50.

The Converter operates as follows. ,

In blocks 17 and 18, the codes and polar signs of the nodal points of the abscissa and ordinates of the transformation function i (x;) are entered into the blocks and the signs of the positive polarity correspond to the zero code of the sign bit, and to the negative one - one.

The output code of the reversible counter 14 of the address, the width of which is determined by the number of approximation sections, contains the ordinate codes and the abscissas of the corresponding value of the conversion function. The totalizers 8 and 16 determine the result of the codes between the received and previous ordinates and the abscissas, respectively .

With the help of dividing unit 11 and controlled frequency divider 6, the inclination coefficient of the interpolating segments is automatically set, and the frequency divider transfer coefficient 6 at each approximation interval is proportional to the ratio

where y ;, and y; - the previous and incoming values of the ordinate X ;, and X; - previous and incoming abscissa values.

Using the subtraction unit 3, the instant of stopping the reproduction of the function is determined by the coincidence of the code of the input argument from the output of register 1 of the argument and the code from the output of the reversible counter 19 of the argument. The controlled frequency divider 21 controls the frequency of the pulses fed to the counting input of the counter 19, in accordance with the code difference between the incoming X; and the previous x, -., abscissas.

The state of the flip-flops 25 and 28 of the sign of the ordinate and abscissa codes determines the region of the current ordinate and abscissa codes. In this case, the zero code at the output of the trigger 25 corresponds to a positive ordinate, and a single code - negative. Similarly

3

The state of the trigger 28 determines the abscissa region.

Counter reversal control

.14 and 19 are carried out from outputs 40 and 41 of block 30 in accordance with the connection of signals at its inputs. The reversal of the result counter 7 is controlled by trigger 39 depending on the state of the adder.

.26 modulo two and the signal of the ordinate codes from the output 9 of the adder-subtractor 8. In this case, the zero codes on the outputs 40 and 41 of block 30 correspond to the summation mode of counters 19 and 14, and the single codes - to the subtraction mode

Using the OR element 35 and the trigger 36, the ordinate codes and abscissas of the first nodal point are written to counters 7 and 19 at the moment of receiving the first argument value in register 1, which allows functions not starting from zero to be converted.

Consider the operation of the functional Converter in accordance with figure 3.

In the initial state, the reversible counters 7, 14, and 19, the argument register 1, triggers 25, 28, 36, 39, and 45 are reset. By the zero code of the counter 14 address from the zero cells of the memory blocks 17 and 18, the codes and polar signs of the abscissa and ordinates UD of the first nodal point of the conversion function 1 (x;) are extracted. In this case, the polar signs of the abscissa Xp and ordinates are written respectively

oh oh

triggers 28 and 25 on resolving

signal from the output of the decoders 27 and

24 nil

The output 22 of block 3 contains a comparison signal, which is fed through the element OR 23 to the input of the element AND 5, closed, and to the input of the register 1, allowing reception of the code and the polarity sign of the first value of the argument x. When entering the register 1 argument X | the trigger 36 is switched to one state, and the output 22 of block 3 forms the leading edge of the comparison signal, held at the time of setting the code and the reverse sign of counters 7 and 19. The signal from the trigger trigger 36 is allowed to write to the counters 7 and 19 ordinates ij and abscissas x from blocks 18 and 17 of memory, respectively. Thus, at output 10, summation

756.

The subtractor 8 generates a comparison pulse signal, the duration of which is determined by the time required to set the division factors of frequency dividers 6 and 21. The comparison signal from the input 10 of the subtractor 8 confirms, through the element OR 23, the closed state of the element 5.

The formation of control signs for the reverse of counters 7, 14, and 19 is performed as follows.

The reversal of the counter 14 is controlled from the output 41 of the block 30. At the output 38 of the adder 29 modulo two, a zero code is generated by coinciding the signs of the argument Y and the abscissa Xd. At the output 20 of block 3, a single code is formed corresponding to the difference of the codes x, - Xjj. At the inputs AND of the I-P1I 49 element, the signals from the output 37 of the trigger 28, the output 20 of the block 3 and the output of the element NE 48 coincide, with the result that the trigger 45 is zeroed. Thus, the counter 14 is set to the summation mode.

The reversal of the counter 19 is controlled from the output 40 of the block 30. Coincidentally, the signals at the inputs of the AND-OR element 44 at the output 40 of the block 30 form a single signal, and the counter 19 is set to the subtraction mode.

On the leading edge of the comparison signal C of the output 10 of the subtractor 8, delayed by the delay element 12 at the time of setting the reverse sign, the state of the reversible counter 14 is changed by one. At that, codes and polar signs of abscissa X, and ordinates and the first section of approximation, adders-subtractors 8–16 are calculated from blocks 17 and 18 of memory and calculate codes of differences Y, -urI X, - Xd, respectively. The comparison signal from the output 10 of the subtractor 8 in block 11 of the division calculates the code

Ug9o

Xi-Xo

control of the transmission coefficient of the frequency divider 6; and in the frequency divider 21, the transmission coefficient corresponding to the difference of the codes X is set, - x from the output of the totalizer-calculator 16.

1211

The control of the reversal of the counter 7 is carried out from the output of the trigger 39 to the information input of which the zero code is output from the output 9, the sum of the toor-subtractor 8, corresponding to the difference of codes y, , the trigger 39 is set to the zero state, the transfer of counter 7 to the summation mode.

After arriving at the input of the subtractor 8 of the ordinate code of the first approximation area y, the output 10 of the subtractor 8 produces the falling edge of the comparison signal delayed by the time required to set the transfer factors of frequency dividers 6 and 21. Element 5 opens on the falling edge of the comparison signal, and the pulses from the generator 4 output arrive at the counting inputs of counters 7 and 19. Stepwise linear interpolation of the function begins in the first approximation area, and the frequency of the pulses on the counting inputs of frequency counters 7 and 19 is determined the division ratio of the dividers is 6 and 21 frequencies, respectively.

When the counter 7 reaches the ordinate code m, the output of the subtractor 8 is formed at the output 10 of the comparing signal, by which the And 5 element is closed. Due to the fact that the state of the signals at the output 20 of block 3, at the output 38 of the adder 29 and at the output 37 of the trigger 28 is not

14 and 19 remain the same and pulse generator 42 does not work. Thus, the state of the address counter 14, delayed by the delay element 12, is changed by one along the leading edge of the pulse from the output 10 of the adder-subtractor 8, and the codes 17 and 18 are extracted from the memory blocks 17 and 18

polar signs of abscissa x and ordinate and the next nodal point. According to the change in the state at the output of the polarity sign of the block 18, the pulse shaper 31 is activated and switches the adder-subtractor 8 to the calculation time of the division factor of the frequency divider 6 to the summing mode. In the subtractor 16 is calculated

x code difference

which 755

carries divider 21 frequencies,

1 1. division calculates code

,

Y, + X

one.

0

five

0

five

0

five

0

0

which is entered into frequency divider 6.

By a single code from the polarity of the block 18, the adder 26 modulo two is set to one state,. Thus, the flip-flop 39 is set to the single state and the counter 7 operates in the subtraction mode. On the falling edge of the comparison signal from the output 10 of the adder-subtractor 8, delayed by the time of setting the division factors of the dividers 6 and 21 of the frequency, the element 5 opens and the reproduction of the second approximation section begins. When the counter 7 reaches the zero code, a trigger is sent to the trigger synchronization input 25 from the output of the decoder 24, which triggers the single code to the trigger 25. At the same time, a zero code is set at the output of the adder 26, which allows writing 39 characters of the difference code from the output 9 of the subtractor 8 to the flip-flop. Thus, a zero signal is set at the output of the flip-flop 39, and the counter 7 starts operating in the summation mode. When counter 7 reaches the nodal point y 2, the second approximation segment finishes playing, and at the output 10 of the subtractor 8, the next pulse comparison signal is generated. The reproduction of the subsequent approximation sections occurs in a similar way.

When counter 7 reaches the ordinate code tj, output 10 of the subtractor 8 forms the next leading edge of the comparison signal, according to which element AND 5 is closed. Signal states at the inputs of block 30 remain the same, and therefore the reverse signs of counters 14 and 19 do not change, and the address counter 14, on the leading edge of the comparison signal, transitions to the next state. From blocks 17 and 18 of the memory, the codes and polar signs of the abscissa rtn-t ordinates y,.,. By changing the state at the outputs of the polarity sign of the blocks 17 and 18, the pulse shapers 33 and 31 and the adders 16 and 8, respectively, are switched to the calculation time of the division coefficients in the summation.

In the subtractor 16, the sum of the codes Xj + x is calculated. , determining the transfer coefficient of the frequency divider 21, and in block dividing code 11

about m y mf 1

Determining transfer coefficient of frequency divider 6.

The polarity sign of the ordinate, the modulator 26 modulo two is set to one, and it in turn translates trigger 39 into one state. Thus, counter 7 operates in subtraction mode.

On the falling edge of the signal from the output 10 of the adder-subtractor 8, delayed by the time of setting the division factors of the dividers 6 and 21 of the frequency, the element And 5 is opened and the function starts to be played in this area of the simulation.

When the counter 19 reaches the argument code x i, the output front of the comparison signal is formed at the output 22 of the block 3, the closing element I 5 and allowing reception in register 1 of the code and the polarity sign of the next argument X,. The zero sign code of the polarity of the argument x changes from zero to one output code of adder 29 modulo two. In block 30, the control signs for the reversal of the counters 14 and 19 are formed. At the inputs of the AND-OR 49 element, the signals from the output 37 of the trigger 28 and the output 38 of the adder 29 coincide, confirming the zero state of the trigger 45, and therefore the mode the summation of the counter 14. According to a single code from the output 38 of the adder 29, arriving at the inputs of the second element AND of the AND-OR 44 element, in the counter 19 is confirmed by sharp subtraction. The reverse of counter 7 remains the same. At the falling edge of the comparison signal from the output 22 of block 3, delayed by the time of setting the signs of the reverse of the counters 7, 14 and 19, opened j

Yu

20

thirty

j,

55 is element 5 and continues to go on. the product of the function in this area of approximation.

When the counter 7 reaches the zero code, the zero polarity sign code tjivi is written to the trigger 25, which leads to the installation of two zero codes modulo two at the output of the adder 26 and, accordingly, writing zero code to the trigger 39 from the output 9 of the adder-subtractor 8. Thus, the counter 7 starts operating in the summation mode.

When the counter 19 reaches the zero code, the trigger 28 records the zero polarity sign code of the abscissa x., Which results in the installation at the output of the adder 29 modulo two zero codes. The presence of a zero code at the output 20 of block 3 causes a zero signal at the output 40 of block 30, and the counter 19 starts operating in the summation mode.

When counter 19 reaches the argument code x, the leading edge of the comparison signal is formed at the output 22 of block 3, the closing element AND 5 and allowing reception in register 1 of the code and polarity sign of the next argument. At the output 20 of block 3, the sign of the difference of codes is formed, which in block 30 the control signs for the reverse of the counters 14 and 19 are set. In this case, the signals at the inputs of the AND-OR 44 element coincide and the counter 19 is set to the subtraction mode. At the inputs of the AND-OR element 50, the signals coincide, and the trigger 45 is set to one, the transfer of counter 14 to the subtraction mode. The change in state at the output 41 of block 30 triggers the pulse generator 42, the output connected to the counting input of the address counter 14. Thus, codes and polarity signs of abscissa X and ordinates y are extracted from memory block 17 and 18. By the unit code of the ordinate polarity, a unit code is set at the output of the adder 26, and accordingly, the trigger 39 goes into one state, and the counter 7 - in subtraction mode.

On the falling edge of the comparison signal from the output 22 of block 3, delayed by the installation time of the characters for the reverse of the counters, the element 5 opens and the testing of the incoming argument X begins. When the counter 19 reaches the XK + argument code, the output 22 of block 3 generates the leading edge of the next comparison signal, the AND 5 element which allows the reception in register 1 of the code and the polarity sign of the next argument X. j In accordance with the polarity sign of the argument Xk + e, the output of the adder 29 modulo two appears a single signal, which through the AND-OR element 44 confirms the subtraction mode of the counter 19. The coincidence of the signals at the inputs of the element AND-OR 50 from the output 38 of the adder 29 and the output of the element 46 confirms the single state of the trigger 45 and, accordingly, the subtraction mode of the counter 14. On the falling edge of the comparison signal from the output 22 of block 3, the element 5 opens and the testing of the received argument K + 3 begins

When the counter 19 reaches the zero code, the unit 28 records the unit code of the polar abscissa X. This results in a zero code at the output of the adder 29 and the absence of signals at the inputs of the AND-OR 44 element. Thus, the counter 19 begins to operate in the summation mode. The coincidence of the signals at the inputs of the I-SHSh 50 element confirms the single state of the trigger 45 and the subtraction mode of the counter 14.

When the counter 7 reaches the zero code, the unit code of the polarity sign of the ordinate y is written to the trigger 25, and the zero code is set at the output of the adder 26. In the trigger 39, the zero code from the output 9 of the adder-subtractor B is written, and the counter 7 starts operating in the summation mode.

When counter 7 reaches the ordinate code Ij, at output 10 of subtractor 8, the leading edge of the comparison signal is formed, according to which element 5 is closed. The state of the signals at the inputs of block 30 remains the same, and therefore the reverse signs of counters 14 and 19, and the address counter 14 on the leading edge of the comparison signal goes to the next State. Codes and polar signs of abscissas x f and ordinates are extracted from memory block 17 and 18.).,. In the frequency divider 6 and 21, the corresponding division 5 is inserted into the division factors on this approximation area. On the falling edge of the comparison signal from the output 10 of the adder-subtractor 8, the element 5 opens, and the processing of the argument of the subsequent approximation sections continues, the device works in a similar way.

Thus, in the proposed 15 functional converter, in comparison with the known device, the class of reproducible functions is expanded due to stepwise linear interpolation of functions depending on 20 on the code and polarity sign of the argument received, and functions starting from an arbitrary value are also reproduced.

25

Claims (1)

Invention Formula A functional converter containing a pulse generator, the first and second controlled frequency dividers, the reversible counter of the argument, the reversible counter of the result, the reversible counter of the address, the memory of nodal points of the ordinates, the memory of nodal points of the abscissa, the dividing unit, the subtraction of the argument, first argument argument the element And, the delay element and the first element OR, and the output of the pulse generator is connected to the first input of the first element And, the output of which connected to the information inputs of the first and second controlled frequency dividers, the outputs of which are connected respectively to the counting inputs of the reversible result counters and the argument, the information input of the converter is connected to the information input of the register of the argument, the output of which is connected to the input of the decremented block of the subtraction of the argument, the output of the characteristic zero of which is connected to the first input of the first element OR, the output of which is connected to the second input of the first element AND, the output of the reverse address counter is connected with the address inputs of the nodal points of the abscissa and ordinates, the output of the dividing unit is connected to the control input of the first control unit) of the time divider, the information output of the reversible counter of results is connected to the output of the converter, the output of the reversible counter of the argument is connected to the input The readable block of the subtraction of the argument, characterized in that, in order to expand the functionality by converting the alternating functions in all four quadrants, totalizers-subtractors are introduced into it ss and ordinates, two modulo adders, a meter control unit, two zero decoders, four flip-flops, second and third OR elements, three pulse makers, and a second and third And elements, with the output of the memory of nodal points of the ordinates connected to the first information input summator-subtractor ordinat. And the installation input of the reversible counter of the result, the output of which is connected to the input of the first decoder zero and the second information input of the sum-torus subtractor of ordinate, the output of the sign zero which is connected to - the receiving input of the division unit, the first inputs of the second and third elements AND, the second input of the first OR element, the input of the delay element and the enabling input of the second controlled frequency divider, the control input of which is connected to the information output of the accumulator-abscissa reader and the input of the divider unit dividing, the input of the dividend of which is connected to the information output of the adder-subtractor of ordinates, the output of the sign of the code of which is connected to the information input of the first trigger, the synchronization and setting inputs of which Connected to the output of the first modulo-two adder, the first input of which is connected to the output of the second trigger, the synchronization input of which is connected to the output of the first decoder zero, the output of the polarity sign of the memory block of the nodal points of the second trigger, the second input of the first modulo two and the input of the first pulse generator, the output of which is connected to the second input of the third element And whose output is connected to the control input of the adder-subtractor of ordinates, the outputs of the yes argument register are connected to inputs of the second 21175612 the OR element, the output of which is connected to the installation input of the third trigger, the output of which is connected to the recording resolution inputs of the reversible 5 argument and result counters, the output of the first trigger is connected to the control input of the reversible result counter, the output of the sign unit of the argument subtraction 10 is connected to the first input of the billing direction of the meter control unit, the first output of which is connected to the control input of the reversible argument counter, the output of which 15 Connected to the first input of the abscissa subtractor and the input of the second decoder zero, the output of which is connected to the synchronization input of the fourth trigger, the output of which is connected to the first input of the second modulo two and the second input of the counting voltage of the counter control unit, the second output of which is connected to the control input of the relay address counter and through the third pulse shaper to the first input of the third OR element, the output of the delay element is connected to the second input of the third OR element, the output to Secondly, it is connected to the counting input of the reverse address counter, the output of the zeroing block of the argument subtractor is connected to the gate of the argument register, the input of the polarity of the argument of the argument is connected to the information input of the converter, and the output of the sign is connected to the second input of the second modulo two, the output of which connected to the third input of the counting control unit counter, the output of the digit of the polarity of the block of the nodal points of the abscissa is connected to the information input of the fourth trigger and The second pulse generator, the output of which is connected to the second input of the second element I, the output of which is connected to the control input of the abscissa adder-subtractor, the second information input of which is connected to the information output of the abscissa nodal points memory and the information input of the reversible argument counter, and the block counter control co55 holds three NOT elements, three I-Ш1И elements and an RS trigger, the first input of the counting direction of the counter control block is connected to the input of the first thirty 35 40 45 50 13 element and with the first inputs of the first groups of the first, second and third elements AND-OR, the inverse output of the first element is NOT connected to the first inputs of the second groups of the first and second elements AND-OR, the second input of the counting direction of the counter control unit is connected to the input of the second element NOT the second input of the first group of the first element is AND-OR, the first input of the third group of the first element is AND-OR, the second input of the second group of the second element is AND-ШШ the inverse output of the second element is NOT connected to the second inputs of the second group of the first ele I-ШШ, the first and third groups of the second element И-ШШ, the third input of the direction 0 five 14 the counter control unit is connected to the input of the third element NOT, with the second inputs of the third groups of the first and second AND-OR elements and with the first and second inputs of the second group of the third AND-OR element, the inverse output of the third element is NOT connected to the third, the first and second inputs the groups of the first and second elements are AND-OR and the second input of the first group of the third element is AND-OR, the outputs of the first and second elements are AND-OR connected to the reset and RS-trigger inputs, respectively, the output of which is connected to the second output of the unit channeling NIN counters whose first output connected to the output of the third element AND-OR. FIG, g Hd Hda- / Xtf4-3 XUP Hj  x   HA- / H / t Compiled by A.Shul pov Editor T. Parfenova Tehred A. Babinets Order 642/54 Edition 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch ShSh Patent, Uzhgorod, Proektna St., 4 Proofreader L. Patay