SG82045A1 - Plasma treatment to enhance inorganic dielectric adhesion to copper - Google Patents
Plasma treatment to enhance inorganic dielectric adhesion to copperInfo
- Publication number
- SG82045A1 SG82045A1 SG9906335A SG1999006335A SG82045A1 SG 82045 A1 SG82045 A1 SG 82045A1 SG 9906335 A SG9906335 A SG 9906335A SG 1999006335 A SG1999006335 A SG 1999006335A SG 82045 A1 SG82045 A1 SG 82045A1
- Authority
- SG
- Singapore
- Prior art keywords
- copper
- plasma treatment
- inorganic dielectric
- dielectric adhesion
- enhance inorganic
- Prior art date
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title 1
- 229910052802 copper Inorganic materials 0.000 title 1
- 239000010949 copper Substances 0.000 title 1
- 238000009832 plasma treatment Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
- H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
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- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/225,530 US6255217B1 (en) | 1999-01-04 | 1999-01-04 | Plasma treatment to enhance inorganic dielectric adhesion to copper |
Publications (1)
Publication Number | Publication Date |
---|---|
SG82045A1 true SG82045A1 (en) | 2001-07-24 |
Family
ID=22845248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG9906335A SG82045A1 (en) | 1999-01-04 | 1999-12-10 | Plasma treatment to enhance inorganic dielectric adhesion to copper |
Country Status (7)
Country | Link |
---|---|
US (3) | US6255217B1 (de) |
JP (1) | JP3398635B2 (de) |
KR (1) | KR100347743B1 (de) |
CN (1) | CN1134049C (de) |
DE (1) | DE19963864A1 (de) |
SG (1) | SG82045A1 (de) |
TW (1) | TW430867B (de) |
Families Citing this family (66)
Publication number | Priority date | Publication date | Assignee | Title |
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US6429120B1 (en) | 2000-01-18 | 2002-08-06 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
JP2001160558A (ja) * | 1999-12-02 | 2001-06-12 | Nec Corp | 半導体装置の製造方法及び製造装置 |
SG125881A1 (en) * | 1999-12-03 | 2006-10-30 | Lytle Steven Alan | Define via in dual damascene process |
US6352938B2 (en) * | 1999-12-09 | 2002-03-05 | United Microelectronics Corp. | Method of removing photoresist and reducing native oxide in dual damascene copper process |
US6420262B1 (en) * | 2000-01-18 | 2002-07-16 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US6376370B1 (en) | 2000-01-18 | 2002-04-23 | Micron Technology, Inc. | Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy |
US6492267B1 (en) * | 2000-02-11 | 2002-12-10 | Micron Technology, Inc. | Low temperature nitride used as Cu barrier layer |
JP2001298028A (ja) * | 2000-04-17 | 2001-10-26 | Tokyo Electron Ltd | 半導体デバイス製造方法 |
JP3440057B2 (ja) * | 2000-07-05 | 2003-08-25 | 唯知 須賀 | 半導体装置およびその製造方法 |
US6846737B1 (en) * | 2000-08-15 | 2005-01-25 | Intel Corporation | Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials |
WO2002029892A2 (en) | 2000-10-03 | 2002-04-11 | Broadcom Corporation | High-density metal capacitor using dual-damascene copper interconnect |
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DE10059143B4 (de) * | 2000-11-29 | 2006-12-28 | Advanced Micro Devices, Inc., Sunnyvale | Oberflächenbehandlungs- und Deckschichtverfahren zur Herstellung einer Kupfergrenzfläche in einem Halbleiterbauteil |
KR100399909B1 (ko) * | 2000-12-29 | 2003-09-29 | 주식회사 하이닉스반도체 | 반도체 소자의 층간 절연막 형성 방법 |
JP4535629B2 (ja) | 2001-02-21 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6387775B1 (en) * | 2001-04-16 | 2002-05-14 | Taiwan Semiconductor Manufacturing Company | Fabrication of MIM capacitor in copper damascene process |
JP2003017564A (ja) * | 2001-07-04 | 2003-01-17 | Fujitsu Ltd | 半導体装置およびその製造方法 |
US6849389B2 (en) * | 2001-07-12 | 2005-02-01 | International Business Machines Corporation | Method to prevent pattern collapse in features etched in sulfur dioxide-containing plasmas |
US6461914B1 (en) * | 2001-08-29 | 2002-10-08 | Motorola, Inc. | Process for making a MIM capacitor |
DE10150822B4 (de) * | 2001-10-15 | 2007-01-25 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Entfernen oxidierter Bereiche auf einer Grenzfläche einer Metalloberfläche |
US6737747B2 (en) * | 2002-01-15 | 2004-05-18 | International Business Machines Corporation | Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof |
US20030134499A1 (en) * | 2002-01-15 | 2003-07-17 | International Business Machines Corporation | Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof |
US6518184B1 (en) * | 2002-01-18 | 2003-02-11 | Intel Corporation | Enhancement of an interconnect |
JP3716218B2 (ja) * | 2002-03-06 | 2005-11-16 | 富士通株式会社 | 配線構造及びその形成方法 |
US6797652B1 (en) * | 2002-03-15 | 2004-09-28 | Advanced Micro Devices, Inc. | Copper damascene with low-k capping layer and improved electromigration reliability |
TW559999B (en) * | 2002-05-08 | 2003-11-01 | Nec Corp | Semiconductor device having silicon-including metal wiring layer and its manufacturing method |
US6847077B2 (en) * | 2002-06-25 | 2005-01-25 | Agere Systems, Inc. | Capacitor for a semiconductor device and method for fabrication therefor |
JP3874268B2 (ja) * | 2002-07-24 | 2007-01-31 | Tdk株式会社 | パターン化薄膜およびその形成方法 |
US6831008B2 (en) * | 2002-09-30 | 2004-12-14 | Texas Instruments Incorporated | Nickel silicide—silicon nitride adhesion through surface passivation |
CN100352036C (zh) * | 2002-10-17 | 2007-11-28 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
JP4606713B2 (ja) * | 2002-10-17 | 2011-01-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR20040051304A (ko) * | 2002-12-12 | 2004-06-18 | 주식회사 하이닉스반도체 | 반도체 소자의 베리어 절연막 형성방법 및 금속 배선형성방법 |
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KR100482180B1 (ko) * | 2002-12-16 | 2005-04-14 | 동부아남반도체 주식회사 | 반도체 소자 제조방법 |
CN100399520C (zh) * | 2002-12-26 | 2008-07-02 | 富士通株式会社 | 具有多层配线结构的半导体装置及其制造方法 |
US20040124420A1 (en) * | 2002-12-31 | 2004-07-01 | Lin Simon S.H. | Etch stop layer |
JP4454242B2 (ja) * | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
DE10335099B4 (de) * | 2003-07-31 | 2006-06-08 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Verbessern der Dickengleichförmigkeit von Siliziumnitridschichten für mehrere Halbleiterscheiben |
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DE10345453B4 (de) * | 2003-09-30 | 2009-08-20 | Infineon Technologies Ag | Verfahren zum Herstellen eines optischen Sensors mit einer integrierten Schichtstapel-Anordnung |
CN1295776C (zh) * | 2003-12-24 | 2007-01-17 | 上海宏力半导体制造有限公司 | 可分别对双镶嵌工艺的中介窗与沟槽进行表面处理的方法 |
US7094705B2 (en) * | 2004-01-20 | 2006-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-step plasma treatment method to improve CU interconnect electrical performance |
US7223692B2 (en) * | 2004-04-30 | 2007-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd | Multi-level semiconductor device with capping layer for improved adhesion |
US7253501B2 (en) * | 2004-08-03 | 2007-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance metallization cap layer |
US20060046502A1 (en) * | 2004-08-27 | 2006-03-02 | Ngo Minh V | Deposition of hard-mask with minimized hillocks and bubbles |
US7138717B2 (en) * | 2004-12-01 | 2006-11-21 | International Business Machines Corporation | HDP-based ILD capping layer |
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-
1999
- 1999-01-04 US US09/225,530 patent/US6255217B1/en not_active Expired - Lifetime
- 1999-12-10 SG SG9906335A patent/SG82045A1/en unknown
- 1999-12-10 KR KR1019990056470A patent/KR100347743B1/ko not_active IP Right Cessation
- 1999-12-13 CN CNB99126150XA patent/CN1134049C/zh not_active Expired - Lifetime
- 1999-12-22 JP JP36394999A patent/JP3398635B2/ja not_active Expired - Lifetime
- 1999-12-24 TW TW088122855A patent/TW430867B/zh not_active IP Right Cessation
- 1999-12-27 US US09/472,346 patent/US6261951B1/en not_active Expired - Lifetime
- 1999-12-30 DE DE19963864A patent/DE19963864A1/de not_active Ceased
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2001
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US6255217B1 (en) | 2001-07-03 |
CN1134049C (zh) | 2004-01-07 |
KR20000052450A (ko) | 2000-08-25 |
US6261951B1 (en) | 2001-07-17 |
TW430867B (en) | 2001-04-21 |
CN1259762A (zh) | 2000-07-12 |
KR100347743B1 (ko) | 2002-08-09 |
DE19963864A1 (de) | 2000-08-10 |
JP2000200832A (ja) | 2000-07-18 |
US6593660B2 (en) | 2003-07-15 |
US20010053591A1 (en) | 2001-12-20 |
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