SG65719A1 - Fully planarized dual damascene metallization using copper line interconnect and selective cvd aluminium plug - Google Patents

Fully planarized dual damascene metallization using copper line interconnect and selective cvd aluminium plug

Info

Publication number
SG65719A1
SG65719A1 SG1997004692A SG1997004692A SG65719A1 SG 65719 A1 SG65719 A1 SG 65719A1 SG 1997004692 A SG1997004692 A SG 1997004692A SG 1997004692 A SG1997004692 A SG 1997004692A SG 65719 A1 SG65719 A1 SG 65719A1
Authority
SG
Singapore
Prior art keywords
dual damascene
copper line
line interconnect
selective cvd
damascene metallization
Prior art date
Application number
SG1997004692A
Other languages
English (en)
Inventor
Liang-Yuh Chen
Ted Guo
Roderick Craig Mosely
Fusen Chen
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of SG65719A1 publication Critical patent/SG65719A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG1997004692A 1996-12-30 1997-12-26 Fully planarized dual damascene metallization using copper line interconnect and selective cvd aluminium plug SG65719A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/778,205 US6537905B1 (en) 1996-12-30 1996-12-30 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug

Publications (1)

Publication Number Publication Date
SG65719A1 true SG65719A1 (en) 1999-06-22

Family

ID=25112616

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997004692A SG65719A1 (en) 1996-12-30 1997-12-26 Fully planarized dual damascene metallization using copper line interconnect and selective cvd aluminium plug

Country Status (6)

Country Link
US (2) US6537905B1 (de)
EP (1) EP0851483A3 (de)
JP (1) JPH10247650A (de)
KR (1) KR100502252B1 (de)
SG (1) SG65719A1 (de)
TW (1) TW466737B (de)

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US7943527B2 (en) * 2008-05-30 2011-05-17 The Board Of Trustees Of The University Of Illinois Surface preparation for thin film growth by enhanced nucleation
US8252653B2 (en) * 2008-10-21 2012-08-28 Applied Materials, Inc. Method of forming a non-volatile memory having a silicon nitride charge trap layer
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Also Published As

Publication number Publication date
KR19980064795A (ko) 1998-10-07
EP0851483A2 (de) 1998-07-01
EP0851483A3 (de) 1999-10-20
KR100502252B1 (ko) 2005-09-26
TW466737B (en) 2001-12-01
US20030161943A1 (en) 2003-08-28
JPH10247650A (ja) 1998-09-14
US7112528B2 (en) 2006-09-26
US6537905B1 (en) 2003-03-25

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