DE69624230T2 - Hohen Spannungen widerstehende Ausgangsstufe - Google Patents

Hohen Spannungen widerstehende Ausgangsstufe

Info

Publication number
DE69624230T2
DE69624230T2 DE69624230T DE69624230T DE69624230T2 DE 69624230 T2 DE69624230 T2 DE 69624230T2 DE 69624230 T DE69624230 T DE 69624230T DE 69624230 T DE69624230 T DE 69624230T DE 69624230 T2 DE69624230 T2 DE 69624230T2
Authority
DE
Germany
Prior art keywords
high voltage
output stage
voltage withstand
withstand output
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69624230T
Other languages
English (en)
Other versions
DE69624230D1 (de
Inventor
Giovanni Campardo
Stefano Zanardi
Carla Golla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69624230D1 publication Critical patent/DE69624230D1/de
Application granted granted Critical
Publication of DE69624230T2 publication Critical patent/DE69624230T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE69624230T 1996-07-24 1996-07-24 Hohen Spannungen widerstehende Ausgangsstufe Expired - Fee Related DE69624230T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96830413A EP0821484B1 (de) 1996-07-24 1996-07-24 Hohen Spannungen widerstehende Ausgangsstufe

Publications (2)

Publication Number Publication Date
DE69624230D1 DE69624230D1 (de) 2002-11-14
DE69624230T2 true DE69624230T2 (de) 2003-02-13

Family

ID=8225971

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69624230T Expired - Fee Related DE69624230T2 (de) 1996-07-24 1996-07-24 Hohen Spannungen widerstehende Ausgangsstufe

Country Status (3)

Country Link
US (1) US6150844A (de)
EP (1) EP0821484B1 (de)
DE (1) DE69624230T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6537905B1 (en) * 1996-12-30 2003-03-25 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US6268759B1 (en) * 1999-11-23 2001-07-31 Texas Instruments Incorporated Low-power 5-volt input/output tolerant circuit with power-down control for a low voltage CMOS crossbar switch
GB2374475B (en) * 2000-12-15 2005-05-11 Micron Technology Inc Input-output buffer circuit and method for avoiding inadvertent conduction of a pull-up transistor
TWI288478B (en) * 2004-08-26 2007-10-11 Realtek Semiconductor Corp High voltage tolerance output stage

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5160855A (en) * 1991-06-28 1992-11-03 Digital Equipment Corporation Floating-well CMOS output driver
DE69412891T2 (de) * 1993-04-19 1999-04-01 Koninkl Philips Electronics Nv Überspannungsschutzschaltung
US5451889A (en) * 1994-03-14 1995-09-19 Motorola, Inc. CMOS output driver which can tolerate an output voltage greater than the supply voltage without latchup or increased leakage current
JP2922424B2 (ja) * 1994-07-13 1999-07-26 松下電器産業株式会社 出力回路
US5576635A (en) * 1995-02-14 1996-11-19 Advanced Micro Devices, Inc. Output buffer with improved tolerance to overvoltage
US5543733A (en) * 1995-06-26 1996-08-06 Vlsi Technology, Inc. High voltage tolerant CMOS input/output circuit
US5574389A (en) * 1995-08-09 1996-11-12 Taiwan Semiconductor Manufacturing Company Ltd. CMOS 3.3 volt output buffer with 5 volt protection
US5721508A (en) * 1996-01-24 1998-02-24 Cypress Semiconductor Corporation 5 Volt tolerant 3.3 volt output buffer

Also Published As

Publication number Publication date
DE69624230D1 (de) 2002-11-14
US6150844A (en) 2000-11-21
EP0821484B1 (de) 2002-10-09
EP0821484A1 (de) 1998-01-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee