SG54404A1 - Semiconductor integrated circuit device having synchronous function with a plurality of external clocks - Google Patents
Semiconductor integrated circuit device having synchronous function with a plurality of external clocksInfo
- Publication number
- SG54404A1 SG54404A1 SG1996011909A SG1996011909A SG54404A1 SG 54404 A1 SG54404 A1 SG 54404A1 SG 1996011909 A SG1996011909 A SG 1996011909A SG 1996011909 A SG1996011909 A SG 1996011909A SG 54404 A1 SG54404 A1 SG 54404A1
- Authority
- SG
- Singapore
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- external clocks
- synchronous function
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US1007296P | 1996-01-30 | 1996-01-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG54404A1 true SG54404A1 (en) | 1998-11-16 |
Family
ID=21743680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG1996011909A SG54404A1 (en) | 1996-01-30 | 1996-12-24 | Semiconductor integrated circuit device having synchronous function with a plurality of external clocks |
Country Status (7)
Country | Link |
---|---|
US (2) | US5835445A (ja) |
JP (1) | JP3768608B2 (ja) |
KR (1) | KR100443103B1 (ja) |
CN (1) | CN1159058A (ja) |
MY (1) | MY127627A (ja) |
SG (1) | SG54404A1 (ja) |
TW (1) | TW378329B (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1139894A (ja) * | 1997-07-23 | 1999-02-12 | Sharp Corp | クロック同期式読み出し専用メモリ |
JP4353324B2 (ja) * | 1999-08-31 | 2009-10-28 | エルピーダメモリ株式会社 | 半導体装置 |
DE19960557B4 (de) * | 1999-12-15 | 2006-09-07 | Infineon Technologies Ag | Integrierter dynamischer Halbleiterspeicher mit zeitlich gesteuertem Lesezugriff |
KR100652362B1 (ko) * | 2000-09-20 | 2006-11-30 | 삼성전자주식회사 | 정상동작에서는 고정된 카스 레이턴시를 갖고테스트시에는 다양한 카스 레이턴시로 테스트 가능한반도체 메모리 장치 |
DE10123594B4 (de) * | 2001-05-15 | 2006-04-20 | Infineon Technologies Ag | Integrierte Halbleiterschaltung mit unterschiedlich häufig geschalteten Transistoren |
US6798711B2 (en) * | 2002-03-19 | 2004-09-28 | Micron Technology, Inc. | Memory with address management |
US7065666B2 (en) | 2003-11-13 | 2006-06-20 | Micron Technology, Inc. | Apparatus and method for generating a delayed clock signal |
KR100680457B1 (ko) * | 2004-05-31 | 2007-02-08 | 주식회사 하이닉스반도체 | 난드 플래시 메모리 소자의 데이터 출력 회로 및 이를이용한 데이터 출력 방법 |
JP4808070B2 (ja) * | 2006-05-18 | 2011-11-02 | 富士通セミコンダクター株式会社 | 半導体メモリおよび半導体メモリの動作方法 |
CN104637522B (zh) * | 2014-12-26 | 2017-09-05 | 北京时代民芯科技有限公司 | 一种脉宽自适应的可配置存储器ip结构 |
US10395702B1 (en) * | 2018-05-11 | 2019-08-27 | Micron Technology, Inc. | Memory device with a clocking mechanism |
CN111710354B (zh) * | 2020-06-17 | 2022-08-19 | 湖南国科微电子股份有限公司 | 一种ddr3的cmd延时补偿方法、装置、设备及介质 |
CN114528019A (zh) * | 2020-11-23 | 2022-05-24 | 深圳比特微电子科技有限公司 | 多比特寄存器、芯片和计算装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0652632B2 (ja) * | 1985-01-23 | 1994-07-06 | 株式会社日立製作所 | ダイナミツク型ram |
KR100214435B1 (ko) * | 1990-07-25 | 1999-08-02 | 사와무라 시코 | 동기식 버스트 엑세스 메모리 |
JP3533227B2 (ja) * | 1992-09-10 | 2004-05-31 | 株式会社日立製作所 | 半導体記憶装置 |
JPH06309868A (ja) * | 1993-04-26 | 1994-11-04 | Hitachi Ltd | 半導体記憶装置 |
KR960004567B1 (ko) * | 1994-02-04 | 1996-04-09 | 삼성전자주식회사 | 반도체 메모리 장치의 데이타 출력 버퍼 |
US5402389A (en) * | 1994-03-08 | 1995-03-28 | Motorola, Inc. | Synchronous memory having parallel output data paths |
US5384737A (en) * | 1994-03-08 | 1995-01-24 | Motorola Inc. | Pipelined memory having synchronous and asynchronous operating modes |
US5652724A (en) * | 1994-12-23 | 1997-07-29 | Micron Technology, Inc. | Burst EDO memory device having pipelined output buffer |
-
1996
- 1996-08-12 JP JP21242396A patent/JP3768608B2/ja not_active Expired - Fee Related
- 1996-09-12 TW TW085111154A patent/TW378329B/zh not_active IP Right Cessation
- 1996-09-16 US US08/714,465 patent/US5835445A/en not_active Expired - Fee Related
- 1996-10-10 MY MYPI96004212A patent/MY127627A/en unknown
- 1996-11-20 CN CN96121717A patent/CN1159058A/zh active Pending
- 1996-12-24 SG SG1996011909A patent/SG54404A1/en unknown
-
1997
- 1997-01-13 KR KR1019970000629A patent/KR100443103B1/ko not_active IP Right Cessation
-
1998
- 1998-07-27 US US09/123,005 patent/US5886918A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH09213067A (ja) | 1997-08-15 |
CN1159058A (zh) | 1997-09-10 |
KR100443103B1 (ko) | 2004-11-03 |
US5886918A (en) | 1999-03-23 |
TW378329B (en) | 2000-01-01 |
JP3768608B2 (ja) | 2006-04-19 |
KR970060231A (ko) | 1997-08-12 |
MY127627A (en) | 2006-12-29 |
US5835445A (en) | 1998-11-10 |
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