SG43396A1 - Method and apparatus for generating dc-free sequences - Google Patents

Method and apparatus for generating dc-free sequences

Info

Publication number
SG43396A1
SG43396A1 SG1996010437A SG1996010437A SG43396A1 SG 43396 A1 SG43396 A1 SG 43396A1 SG 1996010437 A SG1996010437 A SG 1996010437A SG 1996010437 A SG1996010437 A SG 1996010437A SG 43396 A1 SG43396 A1 SG 43396A1
Authority
SG
Singapore
Prior art keywords
generating
free sequences
sequences
free
Prior art date
Application number
SG1996010437A
Other languages
English (en)
Inventor
Emina Soljanin
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Publication of SG43396A1 publication Critical patent/SG43396A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Dc Digital Transmission (AREA)
  • Error Detection And Correction (AREA)
SG1996010437A 1995-08-15 1996-08-12 Method and apparatus for generating dc-free sequences SG43396A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/515,445 US5608397A (en) 1995-08-15 1995-08-15 Method and apparatus for generating DC-free sequences

Publications (1)

Publication Number Publication Date
SG43396A1 true SG43396A1 (en) 1997-10-17

Family

ID=24051375

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996010437A SG43396A1 (en) 1995-08-15 1996-08-12 Method and apparatus for generating dc-free sequences

Country Status (7)

Country Link
US (1) US5608397A (ru)
EP (1) EP0758825B1 (ru)
JP (2) JP3590209B2 (ru)
KR (1) KR100446878B1 (ru)
CA (1) CA2182428C (ru)
DE (1) DE69603053T2 (ru)
SG (1) SG43396A1 (ru)

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DE69628172T2 (de) * 1995-08-03 2004-04-01 Seagate Technology Llc, Scotts Valley Verfahren zum Kodieren eines Eingabewertes für die Übertragung auf Partial-Response Kanälen
US5960041A (en) * 1995-09-21 1999-09-28 Lucent Technologies Inc. Method and apparatus for generating high rate codes for recording information on a magnetic medium
US5859601A (en) * 1996-04-05 1999-01-12 Regents Of The University Of Minnesota Method and apparatus for implementing maximum transition run codes
JP2853672B2 (ja) * 1996-09-11 1999-02-03 日本電気株式会社 演算処理装置
JP3704358B2 (ja) * 1996-07-03 2005-10-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ ディジタル情報信号の送信および受信
US6233289B1 (en) * 1996-07-17 2001-05-15 Seagate Technolgy, Inc. High rate trellis code for partial response channels
US5910969A (en) * 1996-11-05 1999-06-08 Lucent Technologies Inc. Method of detecting DC-free sequences
US5996110A (en) * 1996-12-16 1999-11-30 Motorola, Inc. Method and apparatus for decoding a data packet
IL131921A0 (en) * 1997-04-08 2001-03-19 Motorola Inc System and method for spectrally shaping transmitted data signals
US6343101B1 (en) * 1998-01-16 2002-01-29 Ess Technology, Inc. Frame-based sign inversion method and system for spectral shaping for pulse-coded-modulation modems
EP1057268A1 (en) * 1998-12-21 2000-12-06 Koninklijke Philips Electronics N.V. Device for encoding n-bit source words into corresponding m-bit channel words and decoding m-bit channel words into corresponding n-bit source words
HUP0103219A3 (en) 1998-12-21 2002-02-28 Koninkl Philips Electronics Nv Device and method for encoding n-bit source words into correspo
US6140947A (en) * 1999-05-07 2000-10-31 Cirrus Logic, Inc. Encoding with economical codebook memory utilization
US6456208B1 (en) * 2000-06-30 2002-09-24 Marvell International, Ltd. Technique to construct 32/33 and other RLL codes
US6504493B1 (en) 2000-10-31 2003-01-07 Marvell International, Ltd. Method and apparatus for encoding/decoding data
US6661356B1 (en) 2001-03-05 2003-12-09 Marvell International, Ltd. Method and apparatus for DC-level constrained coding
US7286065B1 (en) 2001-03-05 2007-10-23 Marvell International Ltd. Method and apparatus for DC-level constrained coding
CN1305220C (zh) * 2001-07-09 2007-03-14 希捷科技有限公司 用于抑制数字数据内低频含量的方法和装置
US6917313B1 (en) 2002-01-16 2005-07-12 Marvell International Ltd. DC-free codes
JP4351156B2 (ja) 2002-06-20 2009-10-28 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｄｃ制御のためのバランスがとられたディスパリティチャネルコード
JP3757918B2 (ja) * 2002-08-20 2006-03-22 日本電気株式会社 符号化変調方法および変調装置、復調方法および復調装置
US6867713B2 (en) * 2002-09-09 2005-03-15 Seagate Technology Llc DC free code design with state dependent mapping
WO2005020440A1 (en) * 2003-08-13 2005-03-03 Seagate Technology Llc Dc-free code design with increased distance between code words
US6989776B2 (en) * 2003-11-17 2006-01-24 Seagate Technology Llc Generation of interleaved parity code words having limited running digital sum values
US7002492B2 (en) * 2004-07-07 2006-02-21 Seagate Technology Llc High rate running digital sum-restricted code
JP2008508649A (ja) * 2004-07-27 2008-03-21 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ ３つ以上の信号レベルを使用するデータワードのエンコーディング
US8139628B1 (en) 2005-01-10 2012-03-20 Marvell International Ltd. Method and device to compensate for baseline wander
US7672387B2 (en) 2005-12-05 2010-03-02 Intel Corporation Multiple input, multiple output wireless communication system, associated methods and data structures
US10917109B1 (en) * 2020-03-06 2021-02-09 Centre National De La Recherche Scientifique Methods for storing digital data as, and for transforming digital data into, synthetic DNA

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JPS57170652A (en) * 1981-04-15 1982-10-20 Nec Corp Transmitting system for burst signal
US4833471A (en) * 1984-03-26 1989-05-23 Canon Kabushiki Kaisha Data processing apparatus
JPS6171751A (ja) * 1984-09-14 1986-04-12 Victor Co Of Japan Ltd 伝送信号送受信回路
JP2578754B2 (ja) * 1985-06-13 1997-02-05 松下電器産業株式会社 デイジタルデ−タ記録方法
US5016258A (en) * 1988-06-10 1991-05-14 Matsushita Electric Industrial Co., Ltd. Digital modulator and demodulator
US5438621A (en) * 1988-11-02 1995-08-01 Hewlett-Packard Company DC-free line code and bit and frame synchronization for arbitrary data transmission
US5022051A (en) * 1988-11-02 1991-06-04 Hewlett-Packard Company DC-free line code for arbitrary data transmission
JP2809832B2 (ja) * 1990-07-13 1998-10-15 株式会社東芝 符号変調方法
JPH04225625A (ja) * 1990-12-27 1992-08-14 Sony Corp ディジタル変調方式
JP3334810B2 (ja) * 1992-02-14 2002-10-15 ソニー株式会社 符号化方法、再生方法、および、再生装置
JPH05284035A (ja) * 1992-03-31 1993-10-29 Sony Corp 情報変換方法
JP3083011B2 (ja) * 1992-12-28 2000-09-04 キヤノン株式会社 データ記録方法及び装置
US5341134A (en) * 1992-12-30 1994-08-23 Datatape Incorporated Simple coding scheme for DC free channel codes of form M/N, where M=N-1 and M and N are positive integers
US5477222A (en) * 1993-05-04 1995-12-19 U.S. Philips Corporation Device for encoding/decoding N-bit source words into corresponding M-bit channel words, and vice versa
JP3240341B2 (ja) * 1993-07-06 2001-12-17 三菱電機株式会社 情報変換方法及び記録再生装置
US5450443A (en) * 1993-09-01 1995-09-12 International Business Machines Corporation Method and apparatus for constructing asymptotically optimal second order DC-free channel codes

Also Published As

Publication number Publication date
CA2182428A1 (en) 1997-02-16
CA2182428C (en) 2000-06-13
US5608397A (en) 1997-03-04
DE69603053D1 (de) 1999-08-05
EP0758825B1 (en) 1999-06-30
JP2002335160A (ja) 2002-11-22
KR100446878B1 (ko) 2005-01-27
KR970012100A (ko) 1997-03-29
JPH09121169A (ja) 1997-05-06
JP3590209B2 (ja) 2004-11-17
DE69603053T2 (de) 1999-12-09
EP0758825A1 (en) 1997-02-19

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