SG182670A1 - Method of reducing pattern collapse in high aspect ratio nanostructures - Google Patents

Method of reducing pattern collapse in high aspect ratio nanostructures Download PDF

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Publication number
SG182670A1
SG182670A1 SG2012054318A SG2012054318A SG182670A1 SG 182670 A1 SG182670 A1 SG 182670A1 SG 2012054318 A SG2012054318 A SG 2012054318A SG 2012054318 A SG2012054318 A SG 2012054318A SG 182670 A1 SG182670 A1 SG 182670A1
Authority
SG
Singapore
Prior art keywords
wafer
primer
nanostructures
features
sidewalls
Prior art date
Application number
SG2012054318A
Other languages
English (en)
Inventor
Amir A Yasseri
Ji Zhu
Seokmin Yun
David S L Mui
Katrina Mikhaylichenko
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of SG182670A1 publication Critical patent/SG182670A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02054Cleaning before device manufacture, i.e. Begin-Of-Line process combining dry and wet cleaning steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046Dry cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
SG2012054318A 2010-02-01 2011-01-21 Method of reducing pattern collapse in high aspect ratio nanostructures SG182670A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/697,862 US8617993B2 (en) 2010-02-01 2010-02-01 Method of reducing pattern collapse in high aspect ratio nanostructures
PCT/US2011/022075 WO2011094132A2 (en) 2010-02-01 2011-01-21 Method of reducing pattern collapse in high aspect ratio nanostructures

Publications (1)

Publication Number Publication Date
SG182670A1 true SG182670A1 (en) 2012-08-30

Family

ID=44320060

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2012054318A SG182670A1 (en) 2010-02-01 2011-01-21 Method of reducing pattern collapse in high aspect ratio nanostructures

Country Status (7)

Country Link
US (1) US8617993B2 (enExample)
JP (1) JP5805105B2 (enExample)
KR (1) KR101827020B1 (enExample)
CN (1) CN102741984B (enExample)
SG (1) SG182670A1 (enExample)
TW (1) TWI571925B (enExample)
WO (1) WO2011094132A2 (enExample)

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Also Published As

Publication number Publication date
WO2011094132A2 (en) 2011-08-04
JP2013519217A (ja) 2013-05-23
US20110189858A1 (en) 2011-08-04
JP5805105B2 (ja) 2015-11-04
TWI571925B (zh) 2017-02-21
KR20120116457A (ko) 2012-10-22
KR101827020B1 (ko) 2018-03-22
CN102741984A (zh) 2012-10-17
US8617993B2 (en) 2013-12-31
CN102741984B (zh) 2015-05-13
TW201140682A (en) 2011-11-16
WO2011094132A3 (en) 2011-10-13

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