SG178765A1 - Method for manufacturing soi substrate and semiconductor device - Google Patents

Method for manufacturing soi substrate and semiconductor device Download PDF

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Publication number
SG178765A1
SG178765A1 SG2012008991A SG2012008991A SG178765A1 SG 178765 A1 SG178765 A1 SG 178765A1 SG 2012008991 A SG2012008991 A SG 2012008991A SG 2012008991 A SG2012008991 A SG 2012008991A SG 178765 A1 SG178765 A1 SG 178765A1
Authority
SG
Singapore
Prior art keywords
single crystal
substrate
crystal semiconductor
etching
semiconductor layer
Prior art date
Application number
SG2012008991A
Other languages
English (en)
Inventor
Noda Kosei
Original Assignee
Semiconductor Energy Lab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Lab filed Critical Semiconductor Energy Lab
Publication of SG178765A1 publication Critical patent/SG178765A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SG2012008991A 2009-01-21 2010-01-05 Method for manufacturing soi substrate and semiconductor device SG178765A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009011425 2009-01-21

Publications (1)

Publication Number Publication Date
SG178765A1 true SG178765A1 (en) 2012-03-29

Family

ID=42337296

Family Applications (2)

Application Number Title Priority Date Filing Date
SG2012008991A SG178765A1 (en) 2009-01-21 2010-01-05 Method for manufacturing soi substrate and semiconductor device
SG201000047-9A SG163481A1 (en) 2009-01-21 2010-01-05 Method for manufacturing soi substrate and semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG201000047-9A SG163481A1 (en) 2009-01-21 2010-01-05 Method for manufacturing soi substrate and semiconductor device

Country Status (4)

Country Link
US (2) US8053332B2 (enExample)
JP (1) JP5667767B2 (enExample)
KR (1) KR101661705B1 (enExample)
SG (2) SG178765A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150108428A (ko) 2011-04-11 2015-09-25 에베 그룹 에. 탈너 게엠베하 가요성의 캐리어 마운트 및 캐리어 기판을 분리하기 위한 장치 및 방법
FR2978604B1 (fr) 2011-07-28 2018-09-14 Soitec Procede de guerison de defauts dans une couche semi-conductrice
JP5797504B2 (ja) * 2011-09-16 2015-10-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
EP2795669B1 (de) 2011-12-22 2020-06-17 EV Group E. Thallner GmbH Biegsame substrathalterung, vorrichtung und verfahren zum lösen eines ersten substrats
US8842358B2 (en) 2012-08-01 2014-09-23 Gentex Corporation Apparatus, method, and process with laser induced channel edge
US9029809B2 (en) * 2012-11-30 2015-05-12 Ultratech, Inc. Movable microchamber system with gas curtain
WO2021241448A1 (ja) * 2020-05-29 2021-12-02 株式会社Kokusai Electric 半導体装置の製造方法、基板処理方法、基板処理装置、およびプログラム

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* Cited by examiner, † Cited by third party
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JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Soi基板の製造方法
US5166097A (en) * 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
JP3649797B2 (ja) * 1995-12-01 2005-05-18 株式会社半導体エネルギー研究所 半導体装置製造方法
JP3324469B2 (ja) 1997-09-26 2002-09-17 信越半導体株式会社 Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US5968847A (en) * 1998-03-13 1999-10-19 Applied Materials, Inc. Process for copper etch back
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
US6423644B1 (en) * 2000-07-12 2002-07-23 Applied Materials, Inc. Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures
KR100567885B1 (ko) * 2003-12-30 2006-04-04 동부아남반도체 주식회사 반도체 소자의 실리사이드막 제조 방법
JP5110772B2 (ja) * 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
JP2005251912A (ja) * 2004-03-03 2005-09-15 Seiko Epson Corp 複合半導体基板の製造方法、複合半導体基板、電気光学装置および電子機器
JP5127176B2 (ja) * 2005-07-29 2013-01-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
KR101400699B1 (ko) * 2007-05-18 2014-05-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판 및 반도체 장치 및 그 제조 방법
JP5415676B2 (ja) * 2007-05-30 2014-02-12 信越化学工業株式会社 Soiウェーハの製造方法
CN101681807B (zh) * 2007-06-01 2012-03-14 株式会社半导体能源研究所 半导体器件的制造方法
JP5527956B2 (ja) * 2007-10-10 2014-06-25 株式会社半導体エネルギー研究所 半導体基板の製造方法
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
JP2009135448A (ja) * 2007-11-01 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体基板の作製方法及び半導体装置の作製方法
US8093136B2 (en) * 2007-12-28 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

Also Published As

Publication number Publication date
KR20100085840A (ko) 2010-07-29
JP5667767B2 (ja) 2015-02-12
JP2010192884A (ja) 2010-09-02
US20100184269A1 (en) 2010-07-22
US8338270B2 (en) 2012-12-25
US8053332B2 (en) 2011-11-08
SG163481A1 (en) 2010-08-30
US20120077330A1 (en) 2012-03-29
KR101661705B1 (ko) 2016-09-30

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