SG160272A1 - Relaxation of a strained material layer with application of a stiffener - Google Patents

Relaxation of a strained material layer with application of a stiffener

Info

Publication number
SG160272A1
SG160272A1 SG200905146-7A SG2009051467A SG160272A1 SG 160272 A1 SG160272 A1 SG 160272A1 SG 2009051467 A SG2009051467 A SG 2009051467A SG 160272 A1 SG160272 A1 SG 160272A1
Authority
SG
Singapore
Prior art keywords
layer
stiffener
application
reflow
partially relaxed
Prior art date
Application number
SG200905146-7A
Other languages
English (en)
Inventor
Oleg Kononchuk
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG160272A1 publication Critical patent/SG160272A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
SG200905146-7A 2008-10-07 2009-07-31 Relaxation of a strained material layer with application of a stiffener SG160272A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0805532A FR2936903B1 (fr) 2008-10-07 2008-10-07 Relaxation d'une couche de materiau contraint avec application d'un raidisseur

Publications (1)

Publication Number Publication Date
SG160272A1 true SG160272A1 (en) 2010-04-29

Family

ID=40622166

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200905146-7A SG160272A1 (en) 2008-10-07 2009-07-31 Relaxation of a strained material layer with application of a stiffener

Country Status (8)

Country Link
US (1) US8067298B2 (zh)
JP (1) JP2010093233A (zh)
KR (1) KR20100039216A (zh)
CN (1) CN101714505B (zh)
DE (1) DE102009036412A1 (zh)
FR (1) FR2936903B1 (zh)
SG (1) SG160272A1 (zh)
TW (1) TW201021127A (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2329517A1 (en) * 2008-09-24 2011-06-08 S.O.I.Tec Silicon on Insulator Technologies Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
US8637383B2 (en) 2010-12-23 2014-01-28 Soitec Strain relaxation using metal materials and related structures
JP5907730B2 (ja) 2008-10-30 2016-04-26 エス・オー・アイ・テック・シリコン・オン・インシュレーター・テクノロジーズ 低減した格子ひずみを備えた半導体材料、同様に包含する半導体構造体、デバイス、および、加工された基板を製造する方法
US8105852B2 (en) * 2010-01-15 2012-01-31 Koninklijke Philips Electronics N.V. Method of forming a composite substrate and growing a III-V light emitting device over the composite substrate
JP5696543B2 (ja) * 2011-03-17 2015-04-08 セイコーエプソン株式会社 半導体基板の製造方法
FR2973157B1 (fr) * 2011-03-25 2014-03-14 Soitec Silicon On Insulator Procédé de réalisation d'ilots de matériau contraint au moins partiellement relaxe
CN104094419A (zh) * 2012-01-31 2014-10-08 索泰克公司 具有电荷载流子的改进分布的光敏器件及其形成方法
US8471243B1 (en) 2012-01-31 2013-06-25 Soitec Photoactive devices with improved distribution of charge carriers, and methods of forming same
FR2992466A1 (fr) 2012-06-22 2013-12-27 Soitec Silicon On Insulator Procede de realisation de contact pour led et structure resultante
FR3063571B1 (fr) * 2017-03-01 2021-04-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat donneur pour la formation de dispositifs optoelectroniques, collection de substrats issus de ce procede
FR3064108B1 (fr) 2017-03-17 2022-12-30 Soitec Silicon On Insulator Substrat de croissance pour la formation de dispositifs optoelectroniques, procede de fabrication d'un tel susbstrat, et utilisation du susbtrat notamment dans le domaine des micro-ecrans d'affichage
FR3079070B1 (fr) 2018-03-13 2020-02-28 Soitec Procede de fabrication d'une pluralite d'ilots semi-conducteurs cristallins presentant une variete de parametres de maille
FR3079071B1 (fr) 2018-03-13 2020-02-28 Soitec Procede de fabrication d'une pluralite d'ilots semi-conducteurs cristallins prensentant une variete de parametres de maille
EP4033531B1 (fr) 2017-03-17 2023-08-02 Soitec Procédé de fabrication d'une pluralité d'îlots semiconducteurs cristallins
FR3075833B1 (fr) * 2017-12-22 2022-05-20 Commissariat Energie Atomique Procede permettant d'obtention d'une couche de nitrure
GB2586862B (en) * 2019-09-06 2021-12-15 Plessey Semiconductors Ltd LED precursor incorporating strain relaxing structure

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3478005B2 (ja) * 1996-06-10 2003-12-10 ソニー株式会社 窒化物系化合物半導体のエッチング方法および半導体装置の製造方法
JPH10321533A (ja) * 1997-05-22 1998-12-04 Tokin Corp ウェーハの製造方法、及び半導体装置
JP3274674B2 (ja) * 2000-05-16 2002-04-15 士郎 酒井 窒化ガリウム系化合物半導体の製造方法
JP2001313259A (ja) * 2000-04-28 2001-11-09 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物系化合物半導体基板の製造方法及び半導体素子
JP2002261075A (ja) * 2001-03-02 2002-09-13 Gakushuin School Corp 窒化ガリウム部材の気相エッチング方法
JP2003017790A (ja) * 2001-07-03 2003-01-17 Matsushita Electric Ind Co Ltd 窒化物系半導体素子及び製造方法
JP2004104056A (ja) * 2002-09-09 2004-04-02 Hosiden Corp 窒化ガリウム系半導体発光素子
FR2851847B1 (fr) * 2003-02-28 2005-10-14 Soitec Silicon On Insulator Relaxation d'une couche mince apres transfert
FR2851848B1 (fr) * 2003-02-28 2005-07-08 Soitec Silicon On Insulator Relaxation a haute temperature d'une couche mince apres transfert
US20040192067A1 (en) * 2003-02-28 2004-09-30 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US7261777B2 (en) * 2003-06-06 2007-08-28 S.O.I.Tec Silicon On Insulator Technologies Method for fabricating an epitaxial substrate
EP1484794A1 (en) * 2003-06-06 2004-12-08 S.O.I. Tec Silicon on Insulator Technologies S.A. A method for fabricating a carrier substrate
JP4218597B2 (ja) * 2003-08-08 2009-02-04 住友電気工業株式会社 半導体発光素子の製造方法
JP4055763B2 (ja) * 2004-09-30 2008-03-05 豊田合成株式会社 窒化ガリウム系化合物半導体及び半導体基板
EP1681712A1 (en) * 2005-01-13 2006-07-19 S.O.I. Tec Silicon on Insulator Technologies S.A. Method of producing substrates for optoelectronic applications
JP5095244B2 (ja) * 2006-03-20 2012-12-12 株式会社半導体エネルギー研究所 マイクロマシン、およびその作製方法
JP5003033B2 (ja) * 2006-06-30 2012-08-15 住友電気工業株式会社 ＧａＮ薄膜貼り合わせ基板およびその製造方法、ならびにＧａＮ系半導体デバイスおよびその製造方法

Also Published As

Publication number Publication date
FR2936903A1 (fr) 2010-04-09
KR20100039216A (ko) 2010-04-15
US20100087049A1 (en) 2010-04-08
CN101714505B (zh) 2014-05-28
FR2936903B1 (fr) 2011-01-14
TW201021127A (en) 2010-06-01
CN101714505A (zh) 2010-05-26
US8067298B2 (en) 2011-11-29
DE102009036412A1 (de) 2010-04-15
JP2010093233A (ja) 2010-04-22

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