SG151227A1 - Methods of patterning insulating layers using etching techniques that compensate for etch rate variations - Google Patents

Methods of patterning insulating layers using etching techniques that compensate for etch rate variations

Info

Publication number
SG151227A1
SG151227A1 SG200807115-1A SG2008071151A SG151227A1 SG 151227 A1 SG151227 A1 SG 151227A1 SG 2008071151 A SG2008071151 A SG 2008071151A SG 151227 A1 SG151227 A1 SG 151227A1
Authority
SG
Singapore
Prior art keywords
methods
compensate
insulating layers
etch rate
etching techniques
Prior art date
Application number
SG200807115-1A
Other languages
English (en)
Inventor
Park Wan Jae
Hermann Willhelm Wendt
Anthony David Lisi
Kaushik Arun Kumar
Joseph Edward Linville
Ravi Prakash Srivastava
Original Assignee
Chartered Semiconductor Mfg
Samsung Electronics Co Ltd
Infineon Technologies Ag
Ibm
Advanced Micro Devices Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Mfg, Samsung Electronics Co Ltd, Infineon Technologies Ag, Ibm, Advanced Micro Devices Corp filed Critical Chartered Semiconductor Mfg
Publication of SG151227A1 publication Critical patent/SG151227A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG200807115-1A 2007-09-26 2008-09-24 Methods of patterning insulating layers using etching techniques that compensate for etch rate variations SG151227A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/861,478 US8058176B2 (en) 2007-09-26 2007-09-26 Methods of patterning insulating layers using etching techniques that compensate for etch rate variations

Publications (1)

Publication Number Publication Date
SG151227A1 true SG151227A1 (en) 2009-04-30

Family

ID=40472133

Family Applications (2)

Application Number Title Priority Date Filing Date
SG200807115-1A SG151227A1 (en) 2007-09-26 2008-09-24 Methods of patterning insulating layers using etching techniques that compensate for etch rate variations
SG201100478-5A SG169341A1 (en) 2007-09-26 2008-09-24 Methods of patterning insulating layers using etching techniques that compensate for etch rate variations

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG201100478-5A SG169341A1 (en) 2007-09-26 2008-09-24 Methods of patterning insulating layers using etching techniques that compensate for etch rate variations

Country Status (3)

Country Link
US (1) US8058176B2 (ko)
KR (1) KR101560599B1 (ko)
SG (2) SG151227A1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008198659A (ja) * 2007-02-08 2008-08-28 Tokyo Electron Ltd プラズマエッチング方法
US8058176B2 (en) * 2007-09-26 2011-11-15 Samsung Electronics Co., Ltd. Methods of patterning insulating layers using etching techniques that compensate for etch rate variations
US20110312152A1 (en) * 2010-06-16 2011-12-22 Kim Yoon-Hae Methods of Fabricating Integrated Circuit Devices Using Selective Etching Techniques that Account for Etching Distance Variations
US9607943B2 (en) 2015-06-11 2017-03-28 International Business Machines Corporation Capacitors
US10854453B2 (en) 2017-06-12 2020-12-01 Tokyo Electron Limited Method for reducing reactive ion etch lag in low K dielectric etching
KR102503816B1 (ko) 2017-11-20 2023-02-24 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
US11636997B2 (en) * 2020-07-01 2023-04-25 Applied Materials Israel Ltd. Uniform milling of adjacent materials using parallel scanning fib

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2874263B2 (ja) * 1990-03-26 1999-03-24 ソニー株式会社 シリコン化合物系からなる被エッチング膜のエッチング方法
JP2000091308A (ja) 1998-09-07 2000-03-31 Sony Corp 半導体装置の製造方法
US6251791B1 (en) 1999-07-20 2001-06-26 United Microelectronics Corp. Eliminating etching microloading effect by in situ deposition and etching
JP3403372B2 (ja) * 2000-05-26 2003-05-06 松下電器産業株式会社 有機膜のエッチング方法、半導体装置の製造方法及びパターンの形成方法
US6486070B1 (en) * 2000-09-21 2002-11-26 Lam Research Corporation Ultra-high oxide to photoresist selective etch of high-aspect-ratio openings in a low-pressure, high-density plasma
US6893969B2 (en) * 2001-02-12 2005-05-17 Lam Research Corporation Use of ammonia for etching organic low-k dielectrics
US6760529B2 (en) * 2001-12-11 2004-07-06 Intel Corporation Three-dimensional tapered optical waveguides and methods of manufacture thereof
US6900136B2 (en) * 2002-03-08 2005-05-31 Industrial Technology Research Institute Method for reducing reactive ion etching (RIE) lag in semiconductor fabrication processes
US7105098B1 (en) * 2002-06-06 2006-09-12 Sandia Corporation Method to control artifacts of microstructural fabrication
JP4067357B2 (ja) 2002-08-05 2008-03-26 株式会社アルバック エッチング方法
KR20050009799A (ko) 2003-07-16 2005-01-26 매그나칩 반도체 유한회사 듀얼 다마신 공정을 이용한 반도체 소자의 금속 배선 형성방법
CN100517596C (zh) * 2004-06-29 2009-07-22 优利讯美国有限公司 减少时分复用蚀刻工艺中蚀刻纵横比相关度的方法和装置
US7307025B1 (en) * 2005-04-12 2007-12-11 Lam Research Corporation Lag control
JP5082338B2 (ja) * 2006-08-25 2012-11-28 東京エレクトロン株式会社 エッチング方法及びエッチング装置
KR100843236B1 (ko) * 2007-02-06 2008-07-03 삼성전자주식회사 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법
US7629255B2 (en) * 2007-06-04 2009-12-08 Lam Research Corporation Method for reducing microloading in etching high aspect ratio structures
US20090068767A1 (en) * 2007-09-12 2009-03-12 Lam Research Corporation Tuning via facet with minimal rie lag
US8058176B2 (en) * 2007-09-26 2011-11-15 Samsung Electronics Co., Ltd. Methods of patterning insulating layers using etching techniques that compensate for etch rate variations

Also Published As

Publication number Publication date
KR101560599B1 (ko) 2015-10-16
SG169341A1 (en) 2011-03-30
KR20090032013A (ko) 2009-03-31
US8058176B2 (en) 2011-11-15
US20090081873A1 (en) 2009-03-26

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