SG135073A1 - Method and apparatus for cascade memory - Google Patents

Method and apparatus for cascade memory

Info

Publication number
SG135073A1
SG135073A1 SG200601251-2A SG2006012512A SG135073A1 SG 135073 A1 SG135073 A1 SG 135073A1 SG 2006012512 A SG2006012512 A SG 2006012512A SG 135073 A1 SG135073 A1 SG 135073A1
Authority
SG
Singapore
Prior art keywords
memory
cascade
cascade memory
operatively connected
cascade circuit
Prior art date
Application number
SG200601251-2A
Other languages
English (en)
Inventor
Teng Pin Poo
Original Assignee
Trek 2000 Int Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Trek 2000 Int Ltd filed Critical Trek 2000 Int Ltd
Priority to SG200601251-2A priority Critical patent/SG135073A1/en
Priority to EP06784254A priority patent/EP1989711A4/en
Priority to RU2008134388/09A priority patent/RU2008134388A/ru
Priority to BRPI0621373-1A priority patent/BRPI0621373A2/pt
Priority to CN2006800528548A priority patent/CN101375339B/zh
Priority to JP2008556282A priority patent/JP5037535B2/ja
Priority to PCT/SG2006/000235 priority patent/WO2007097712A1/en
Publication of SG135073A1 publication Critical patent/SG135073A1/en
Priority to US12/189,610 priority patent/US8443132B2/en
Priority to KR1020087021510A priority patent/KR101270179B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
SG200601251-2A 2006-02-27 2006-02-27 Method and apparatus for cascade memory SG135073A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
SG200601251-2A SG135073A1 (en) 2006-02-27 2006-02-27 Method and apparatus for cascade memory
EP06784254A EP1989711A4 (en) 2006-02-27 2006-08-17 METHOD AND DEVICE FOR CASCADES MEMORY
RU2008134388/09A RU2008134388A (ru) 2006-02-27 2006-08-17 Способ и устройство для реализации каскадной памяти
BRPI0621373-1A BRPI0621373A2 (pt) 2006-02-27 2006-08-17 método e aparelho para memória em cascata
CN2006800528548A CN101375339B (zh) 2006-02-27 2006-08-17 用于级联存储器的方法及设备
JP2008556282A JP5037535B2 (ja) 2006-02-27 2006-08-17 カスケードメモリのための方法及び装置
PCT/SG2006/000235 WO2007097712A1 (en) 2006-02-27 2006-08-17 Method and apparatus for cascade memory
US12/189,610 US8443132B2 (en) 2006-02-27 2008-08-11 Method and apparatus for cascade memory
KR1020087021510A KR101270179B1 (ko) 2006-02-27 2008-09-02 캐스케이드 메모리를 위한 방법 및 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200601251-2A SG135073A1 (en) 2006-02-27 2006-02-27 Method and apparatus for cascade memory

Publications (1)

Publication Number Publication Date
SG135073A1 true SG135073A1 (en) 2007-09-28

Family

ID=38437655

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200601251-2A SG135073A1 (en) 2006-02-27 2006-02-27 Method and apparatus for cascade memory

Country Status (9)

Country Link
US (1) US8443132B2 (ja)
EP (1) EP1989711A4 (ja)
JP (1) JP5037535B2 (ja)
KR (1) KR101270179B1 (ja)
CN (1) CN101375339B (ja)
BR (1) BRPI0621373A2 (ja)
RU (1) RU2008134388A (ja)
SG (1) SG135073A1 (ja)
WO (1) WO2007097712A1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101715145B (zh) * 2008-10-06 2012-08-15 辉达公司 利用级联存储器评估处理能力的设备和方法
TWI423033B (zh) * 2009-12-22 2014-01-11 Ind Tech Res Inst 可串接之序列匯流排卡裝置及其管理方法及串接方法
WO2015057865A1 (en) 2013-10-15 2015-04-23 Rambus Inc. Load reduced memory module
KR102196087B1 (ko) 2014-01-07 2020-12-30 삼성디스플레이 주식회사 구동 모듈의 동기화 방법 및 이를 수행하는 표시 장치
CN110989921B (zh) * 2019-10-24 2023-05-26 西安艾可萨科技有限公司 可配置存储阵列系统及其控制方法、通信设备

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6379290A (ja) * 1986-09-24 1988-04-09 Hitachi Vlsi Eng Corp 半導体記憶装置
US5430859A (en) * 1991-07-26 1995-07-04 Sundisk Corporation Solid state memory system including plural memory chips and a serialized bus
US5818350A (en) * 1995-04-11 1998-10-06 Lexar Microsystems Inc. High performance method of and system for selecting one of a plurality of IC chip while requiring minimal select lines
US5608342A (en) * 1995-10-23 1997-03-04 Xilinx, Inc. Hierarchical programming of electrically configurable integrated circuits
US5987554A (en) * 1997-05-13 1999-11-16 Micron Electronics, Inc. Method of controlling the transfer of information across an interface between two buses
WO1999023662A1 (en) * 1997-10-30 1999-05-14 Netlogic Microsystems, Inc. Method and apparatus for cascading content addressable memory devices
JP2002007308A (ja) * 2000-06-20 2002-01-11 Nec Corp メモリバスシステムおよび信号線の接続方法
US6779045B2 (en) * 2001-03-21 2004-08-17 Intel Corporation System and apparatus for increasing the number of operations per transmission for a media management system
IL159391A0 (en) * 2001-06-28 2004-06-01 Trek 2000 Int Ltd Method and devices for data transfer
US6657914B1 (en) * 2001-07-19 2003-12-02 Inapac Technology, Inc. Configurable addressing for multiple chips in a package
GB0122479D0 (en) * 2001-09-18 2001-11-07 Anadigm Ltd Method and apparatus for loading data into a plurality of programmable devices
US6912646B1 (en) * 2003-01-06 2005-06-28 Xilinx, Inc. Storing and selecting multiple data streams in distributed memory devices
US7788451B2 (en) * 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US20060036826A1 (en) * 2004-07-30 2006-02-16 International Business Machines Corporation System, method and storage medium for providing a bus speed multiplier
US7265578B1 (en) * 2005-04-04 2007-09-04 Lattice Semiconductor Corporation In-system programming of non-JTAG device using SPI and JTAG interfaces of FPGA device

Also Published As

Publication number Publication date
CN101375339B (zh) 2012-05-30
US20090070522A1 (en) 2009-03-12
US8443132B2 (en) 2013-05-14
JP2009528588A (ja) 2009-08-06
CN101375339A (zh) 2009-02-25
WO2007097712A1 (en) 2007-08-30
KR101270179B1 (ko) 2013-05-31
RU2008134388A (ru) 2010-04-10
EP1989711A1 (en) 2008-11-12
JP5037535B2 (ja) 2012-09-26
KR20080105055A (ko) 2008-12-03
BRPI0621373A2 (pt) 2011-12-06
EP1989711A4 (en) 2009-08-05

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