SG122776A1 - Process for cleaving layers of a wafer of material - Google Patents
Process for cleaving layers of a wafer of materialInfo
- Publication number
- SG122776A1 SG122776A1 SG200300076A SG200300076A SG122776A1 SG 122776 A1 SG122776 A1 SG 122776A1 SG 200300076 A SG200300076 A SG 200300076A SG 200300076 A SG200300076 A SG 200300076A SG 122776 A1 SG122776 A1 SG 122776A1
- Authority
- SG
- Singapore
- Prior art keywords
- cleaving
- wafer
- layers
- cleaving layers
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Element Separation (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Dicing (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0200475A FR2834820B1 (fr) | 2002-01-16 | 2002-01-16 | Procede de clivage de couches d'une tranche de materiau |
Publications (1)
Publication Number | Publication Date |
---|---|
SG122776A1 true SG122776A1 (en) | 2006-06-29 |
Family
ID=8871305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200300076A SG122776A1 (en) | 2002-01-16 | 2003-01-10 | Process for cleaving layers of a wafer of material |
Country Status (8)
Country | Link |
---|---|
US (1) | US6884697B2 (de) |
EP (1) | EP1331663B1 (de) |
JP (1) | JP4698124B2 (de) |
CN (1) | CN1433056B (de) |
DE (1) | DE60324486D1 (de) |
FR (1) | FR2834820B1 (de) |
SG (1) | SG122776A1 (de) |
TW (1) | TWI273647B (de) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (fr) * | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
FR2830983B1 (fr) * | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | Procede de fabrication de couches minces contenant des microcomposants |
FR2847075B1 (fr) * | 2002-11-07 | 2005-02-18 | Commissariat Energie Atomique | Procede de formation d'une zone fragile dans un substrat par co-implantation |
US7176108B2 (en) * | 2002-11-07 | 2007-02-13 | Soitec Silicon On Insulator | Method of detaching a thin film at moderate temperature after co-implantation |
FR2848336B1 (fr) * | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
FR2857953B1 (fr) | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | Structure empilee, et procede pour la fabriquer |
JPWO2005024916A1 (ja) * | 2003-09-05 | 2007-11-08 | 株式会社Sumco | Soiウェーハの作製方法 |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
US7772087B2 (en) * | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
JP5042837B2 (ja) * | 2004-09-21 | 2012-10-03 | ソイテック | 気泡の形成を回避し、かつ、粗さを制限する条件により共注入工程を行う薄層転写方法 |
FR2886051B1 (fr) | 2005-05-20 | 2007-08-10 | Commissariat Energie Atomique | Procede de detachement d'un film mince |
FR2889887B1 (fr) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
FR2891281B1 (fr) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
FR2899378B1 (fr) * | 2006-03-29 | 2008-06-27 | Commissariat Energie Atomique | Procede de detachement d'un film mince par fusion de precipites |
US8293619B2 (en) * | 2008-08-28 | 2012-10-23 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled propagation |
KR101262226B1 (ko) * | 2006-10-31 | 2013-05-15 | 삼성전자주식회사 | 반도체 발광 소자의 제조방법 |
FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
FR2912259B1 (fr) | 2007-02-01 | 2009-06-05 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat du type "silicium sur isolant". |
FR2919960B1 (fr) * | 2007-08-08 | 2010-05-21 | Soitec Silicon On Insulator | Procede et installation pour la fracture d'un substrat composite selon un plan de fragilisation |
FR2922681A1 (fr) * | 2007-10-23 | 2009-04-24 | Soitec Silicon On Insulator | Procede de detachement d'un substrat. |
FR2925221B1 (fr) | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
US8563352B2 (en) * | 2008-02-05 | 2013-10-22 | Gtat Corporation | Creation and translation of low-relief texture for a photovoltaic cell |
US8129613B2 (en) * | 2008-02-05 | 2012-03-06 | Twin Creeks Technologies, Inc. | Photovoltaic cell comprising a thin lamina having low base resistivity and method of making |
US8178419B2 (en) | 2008-02-05 | 2012-05-15 | Twin Creeks Technologies, Inc. | Method to texture a lamina surface within a photovoltaic cell |
US8481845B2 (en) * | 2008-02-05 | 2013-07-09 | Gtat Corporation | Method to form a photovoltaic cell comprising a thin lamina |
US20100032010A1 (en) * | 2008-08-10 | 2010-02-11 | Twin Creeks Technologies, Inc. | Method to mitigate shunt formation in a photovoltaic cell comprising a thin lamina |
US8338209B2 (en) * | 2008-08-10 | 2012-12-25 | Twin Creeks Technologies, Inc. | Photovoltaic cell comprising a thin lamina having a rear junction and method of making |
US20100031995A1 (en) * | 2008-08-10 | 2010-02-11 | Twin Creeks Technologies, Inc. | Photovoltaic module comprising thin laminae configured to mitigate efficiency loss due to shunt formation |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US8198172B2 (en) * | 2009-02-25 | 2012-06-12 | Micron Technology, Inc. | Methods of forming integrated circuits using donor and acceptor substrates |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
US8349626B2 (en) * | 2010-03-23 | 2013-01-08 | Gtat Corporation | Creation of low-relief texture for a photovoltaic cell |
JP5670303B2 (ja) * | 2011-12-08 | 2015-02-18 | 信越半導体株式会社 | イオン注入機の基板保持具の劣化判定方法 |
US10991617B2 (en) | 2018-05-15 | 2021-04-27 | Applied Materials, Inc. | Methods and apparatus for cleaving of semiconductor substrates |
FR3093715B1 (fr) | 2019-03-15 | 2021-03-05 | Soitec Silicon On Insulator | Dispositif de maintien pour un ensemble à fracturer |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0926713A2 (de) * | 1997-12-26 | 1999-06-30 | Canon Kabushiki Kaisha | Anordnung und Verfahren zur Ätzung eines halbleitenden Gegenstand und Methode zur Vorbereitung einer Halbleiteranordnung |
US6100165A (en) * | 1996-11-15 | 2000-08-08 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor article |
EP1045448A1 (de) * | 1998-10-16 | 2000-10-18 | Shin-Etsu Handotai Co., Ltd | Verfahren zur herstellung von einem soi-wafer mittels trennung durch wasserstoffimplantierung und dadurch hergestelltes soi-wafer |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
CA2233115C (en) * | 1997-03-27 | 2002-03-12 | Canon Kabushiki Kaisha | Semiconductor substrate and method of manufacturing the same |
US6540861B2 (en) * | 1998-04-01 | 2003-04-01 | Canon Kabushiki Kaisha | Member separating apparatus and processing apparatus |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
JP2000077287A (ja) * | 1998-08-26 | 2000-03-14 | Nissin Electric Co Ltd | 結晶薄膜基板の製造方法 |
JP4379943B2 (ja) * | 1999-04-07 | 2009-12-09 | 株式会社デンソー | 半導体基板の製造方法および半導体基板製造装置 |
JP4413360B2 (ja) * | 2000-02-22 | 2010-02-10 | 株式会社神戸製鋼所 | 半導体ウエハの処理方法 |
JP2002353082A (ja) * | 2001-05-28 | 2002-12-06 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
-
2002
- 2002-01-16 FR FR0200475A patent/FR2834820B1/fr not_active Expired - Fee Related
-
2003
- 2003-01-10 SG SG200300076A patent/SG122776A1/en unknown
- 2003-01-14 DE DE60324486T patent/DE60324486D1/de not_active Expired - Lifetime
- 2003-01-14 US US10/341,254 patent/US6884697B2/en not_active Expired - Lifetime
- 2003-01-14 EP EP03290087A patent/EP1331663B1/de not_active Expired - Lifetime
- 2003-01-15 TW TW092100743A patent/TWI273647B/zh not_active IP Right Cessation
- 2003-01-16 CN CN03100518.7A patent/CN1433056B/zh not_active Expired - Lifetime
- 2003-01-16 JP JP2003008485A patent/JP4698124B2/ja not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100165A (en) * | 1996-11-15 | 2000-08-08 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor article |
EP0926713A2 (de) * | 1997-12-26 | 1999-06-30 | Canon Kabushiki Kaisha | Anordnung und Verfahren zur Ätzung eines halbleitenden Gegenstand und Methode zur Vorbereitung einer Halbleiteranordnung |
EP1045448A1 (de) * | 1998-10-16 | 2000-10-18 | Shin-Etsu Handotai Co., Ltd | Verfahren zur herstellung von einem soi-wafer mittels trennung durch wasserstoffimplantierung und dadurch hergestelltes soi-wafer |
Also Published As
Publication number | Publication date |
---|---|
FR2834820B1 (fr) | 2005-03-18 |
EP1331663B1 (de) | 2008-11-05 |
JP2003264270A (ja) | 2003-09-19 |
CN1433056A (zh) | 2003-07-30 |
FR2834820A1 (fr) | 2003-07-18 |
JP4698124B2 (ja) | 2011-06-08 |
TWI273647B (en) | 2007-02-11 |
TW200401354A (en) | 2004-01-16 |
DE60324486D1 (de) | 2008-12-18 |
US20030134489A1 (en) | 2003-07-17 |
EP1331663A1 (de) | 2003-07-30 |
US6884697B2 (en) | 2005-04-26 |
CN1433056B (zh) | 2010-05-26 |
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