IL190716A0 - A method for plasma etching - Google Patents
A method for plasma etchingInfo
- Publication number
- IL190716A0 IL190716A0 IL190716A IL19071608A IL190716A0 IL 190716 A0 IL190716 A0 IL 190716A0 IL 190716 A IL190716 A IL 190716A IL 19071608 A IL19071608 A IL 19071608A IL 190716 A0 IL190716 A0 IL 190716A0
- Authority
- IL
- Israel
- Prior art keywords
- plasma etching
- etching
- plasma
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41780602P | 2002-10-11 | 2002-10-11 | |
US10/295,601 US6833325B2 (en) | 2002-10-11 | 2002-11-14 | Method for plasma etching performance enhancement |
US10/674,675 US7169695B2 (en) | 2002-10-11 | 2003-09-29 | Method for forming a dual damascene structure |
PCT/US2003/031712 WO2004034445A2 (en) | 2002-10-11 | 2003-10-06 | A method for plasma etching performance enhancement |
Publications (2)
Publication Number | Publication Date |
---|---|
IL190716A0 true IL190716A0 (en) | 2008-11-03 |
IL190716A IL190716A (en) | 2011-07-31 |
Family
ID=46123508
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL167935A IL167935A (en) | 2002-10-11 | 2005-04-10 | Method for plasma etching |
IL190716A IL190716A (en) | 2002-10-11 | 2008-04-08 | Method for plasma etching |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL167935A IL167935A (en) | 2002-10-11 | 2005-04-10 | Method for plasma etching |
Country Status (5)
Country | Link |
---|---|
KR (1) | KR101075045B1 (en) |
CN (1) | CN1723549B (en) |
IL (2) | IL167935A (en) |
SG (1) | SG152920A1 (en) |
TW (1) | TWI315751B (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7910489B2 (en) * | 2006-02-17 | 2011-03-22 | Lam Research Corporation | Infinitely selective photoresist mask etch |
KR101573949B1 (en) * | 2007-11-08 | 2015-12-02 | 램 리써치 코포레이션 | Pitch reduction using oxide spacer |
CN101983417B (en) * | 2008-03-31 | 2013-04-24 | 日本瑞翁株式会社 | Plasma etching method |
US8277670B2 (en) * | 2008-05-13 | 2012-10-02 | Lam Research Corporation | Plasma process with photoresist mask pretreatment |
CN101988196B (en) * | 2009-08-07 | 2013-09-04 | 中微半导体设备(上海)有限公司 | Deep reactive ion etching method and gas-flow control device thereof |
US8304262B2 (en) * | 2011-02-17 | 2012-11-06 | Lam Research Corporation | Wiggling control for pseudo-hardmask |
US8501499B2 (en) * | 2011-03-28 | 2013-08-06 | Tokyo Electron Limited | Adaptive recipe selector |
US8598040B2 (en) * | 2011-09-06 | 2013-12-03 | Lam Research Corporation | ETCH process for 3D flash structures |
JP6030886B2 (en) * | 2012-08-09 | 2016-11-24 | 東京エレクトロン株式会社 | Plasma etching method and plasma etching apparatus |
JP6320282B2 (en) * | 2014-12-05 | 2018-05-09 | 東京エレクトロン株式会社 | Etching method |
JP6232037B2 (en) * | 2015-12-04 | 2017-11-15 | 株式会社日本トリム | Electrolyzed water generation system |
CN107994026B (en) * | 2017-11-16 | 2020-07-10 | 长江存储科技有限责任公司 | Process for protecting side wall in etching high depth-to-width ratio trench hole |
CN107910294A (en) * | 2017-11-24 | 2018-04-13 | 睿力集成电路有限公司 | The interconnecting construction of semiconductor devices and the interconnection line manufacture method of semiconductor devices |
US10964587B2 (en) * | 2018-05-21 | 2021-03-30 | Tokyo Electron Limited | Atomic layer deposition for low-K trench protection during etch |
CN109524415B (en) * | 2018-11-14 | 2021-03-30 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory and three-dimensional memory |
CN113035694A (en) * | 2019-12-25 | 2021-06-25 | 中微半导体设备(上海)股份有限公司 | Etching method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE251341T1 (en) * | 1996-08-01 | 2003-10-15 | Surface Technology Systems Plc | METHOD FOR ETCHING SUBSTRATES |
US6127258A (en) * | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
US6025255A (en) * | 1998-06-25 | 2000-02-15 | Vanguard International Semiconductor Corporation | Two-step etching process for forming self-aligned contacts |
US6326307B1 (en) * | 1999-11-15 | 2001-12-04 | Appllied Materials, Inc. | Plasma pretreatment of photoresist in an oxide etch process |
US6403491B1 (en) * | 2000-11-01 | 2002-06-11 | Applied Materials, Inc. | Etch method using a dielectric etch chamber with expanded process window |
DE10059836A1 (en) * | 2000-12-01 | 2002-06-13 | Infineon Technologies Ag | Structuring dielectric layer used in semiconductor industry comprises preparing substrate consisting of dielectric layer and mask, and etching dielectric layer |
-
2003
- 2003-10-06 KR KR1020107021194A patent/KR101075045B1/en active IP Right Grant
- 2003-10-06 SG SG200702280-9A patent/SG152920A1/en unknown
- 2003-10-06 CN CN200380105311.4A patent/CN1723549B/en not_active Expired - Lifetime
- 2003-10-09 TW TW092128179A patent/TWI315751B/en not_active IP Right Cessation
-
2005
- 2005-04-10 IL IL167935A patent/IL167935A/en not_active IP Right Cessation
-
2008
- 2008-04-08 IL IL190716A patent/IL190716A/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20100108467A (en) | 2010-10-06 |
KR101075045B1 (en) | 2011-10-19 |
SG152920A1 (en) | 2009-06-29 |
TWI315751B (en) | 2009-10-11 |
TW200408732A (en) | 2004-06-01 |
CN1723549B (en) | 2012-01-18 |
IL167935A (en) | 2009-12-24 |
CN1723549A (en) | 2006-01-18 |
IL190716A (en) | 2011-07-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FF | Patent granted | ||
KB | Patent renewed | ||
KB | Patent renewed | ||
MM9K | Patent not in force due to non-payment of renewal fees |