SG11201806851RA - Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof - Google Patents

Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof

Info

Publication number
SG11201806851RA
SG11201806851RA SG11201806851RA SG11201806851RA SG11201806851RA SG 11201806851R A SG11201806851R A SG 11201806851RA SG 11201806851R A SG11201806851R A SG 11201806851RA SG 11201806851R A SG11201806851R A SG 11201806851RA SG 11201806851R A SG11201806851R A SG 11201806851RA
Authority
SG
Singapore
Prior art keywords
international
semiconductor
pct
insulator structure
low temperature
Prior art date
Application number
SG11201806851RA
Other languages
English (en)
Inventor
Sasha Joseph Kweskin
Original Assignee
Globalwafers Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalwafers Co Ltd filed Critical Globalwafers Co Ltd
Publication of SG11201806851RA publication Critical patent/SG11201806851RA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • Laminated Bodies (AREA)
  • Formation Of Insulating Films (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
SG11201806851RA 2016-03-07 2017-03-03 Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof SG11201806851RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662304376P 2016-03-07 2016-03-07
PCT/US2017/020619 WO2017155805A1 (fr) 2016-03-07 2017-03-03 Structure de semi-conducteur sur isolant contenant une couche d'oxyde fluidifiable à basse température et son procédé de fabrication

Publications (1)

Publication Number Publication Date
SG11201806851RA true SG11201806851RA (en) 2018-09-27

Family

ID=58387889

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201806851RA SG11201806851RA (en) 2016-03-07 2017-03-03 Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof

Country Status (5)

Country Link
US (1) US10593748B2 (fr)
EP (2) EP3427293B1 (fr)
JP (2) JP7002456B2 (fr)
SG (1) SG11201806851RA (fr)
WO (1) WO2017155805A1 (fr)

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* Cited by examiner, † Cited by third party
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WO2017155808A1 (fr) * 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Structure de semi-conducteur sur isolant contenant une couche de nitrure de plasma et son procédé de fabrication
US20180019169A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Backing substrate stabilizing donor substrate for implant or reclamation
CN110085550A (zh) * 2018-01-26 2019-08-02 沈阳硅基科技有限公司 一种半导体产品用绝缘层结构及其制备方法

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Also Published As

Publication number Publication date
JP2019513294A (ja) 2019-05-23
JP2021061413A (ja) 2021-04-15
WO2017155805A1 (fr) 2017-09-14
US10593748B2 (en) 2020-03-17
EP3758050A1 (fr) 2020-12-30
EP3427293B1 (fr) 2021-05-05
EP3427293A1 (fr) 2019-01-16
JP7002456B2 (ja) 2022-01-20
US20190035881A1 (en) 2019-01-31
JP7071486B2 (ja) 2022-05-19

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