SG11201705460VA - Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate - Google Patents

Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate

Info

Publication number
SG11201705460VA
SG11201705460VA SG11201705460VA SG11201705460VA SG11201705460VA SG 11201705460V A SG11201705460V A SG 11201705460VA SG 11201705460V A SG11201705460V A SG 11201705460VA SG 11201705460V A SG11201705460V A SG 11201705460VA SG 11201705460V A SG11201705460V A SG 11201705460VA
Authority
SG
Singapore
Prior art keywords
interconnect
substrate
stacks
interconnects
side portion
Prior art date
Application number
SG11201705460VA
Other languages
English (en)
Inventor
Uei-Ming Jow
Young Kyu Song
Jong-Hoon Lee
Xiaonan Zhang
Mario Francisco Velez
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201705460VA publication Critical patent/SG11201705460VA/en

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    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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    • H01L2924/151—Die mounting substrate
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
SG11201705460VA 2015-02-18 2016-02-17 Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate SG11201705460VA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562117835P 2015-02-18 2015-02-18
US14/703,290 US9691694B2 (en) 2015-02-18 2015-05-04 Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate
PCT/US2016/018345 WO2016134070A1 (en) 2015-02-18 2016-02-17 Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate

Publications (1)

Publication Number Publication Date
SG11201705460VA true SG11201705460VA (en) 2017-09-28

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Application Number Title Priority Date Filing Date
SG11201705460VA SG11201705460VA (en) 2015-02-18 2016-02-17 Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate

Country Status (9)

Country Link
US (1) US9691694B2 (enrdf_load_stackoverflow)
EP (1) EP3259777B1 (enrdf_load_stackoverflow)
JP (1) JP6980530B2 (enrdf_load_stackoverflow)
KR (1) KR102428876B1 (enrdf_load_stackoverflow)
CN (1) CN107251218A (enrdf_load_stackoverflow)
BR (1) BR112017017604B1 (enrdf_load_stackoverflow)
ES (1) ES2877771T3 (enrdf_load_stackoverflow)
SG (1) SG11201705460VA (enrdf_load_stackoverflow)
WO (1) WO2016134070A1 (enrdf_load_stackoverflow)

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US9980378B1 (en) * 2017-03-10 2018-05-22 Dell Products, Lp Surface mount connector pad
US20180350630A1 (en) * 2017-06-01 2018-12-06 Qualcomm Incorporated Symmetric embedded trace substrate
EP3688798A4 (en) * 2017-09-29 2021-05-19 INTEL Corporation SEMI-CONDUCTOR ENCLOSURE WITH EMBEDDED CONNECTIONS
US10916494B2 (en) 2019-01-02 2021-02-09 Qualcomm Incorporated Device comprising first solder interconnects aligned in a first direction and second solder interconnects aligned in a second direction
KR102199602B1 (ko) * 2019-05-29 2021-01-07 주식회사 테토스 기판 회로 패턴 형성용 노광 장치
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WO2016134070A1 (en) 2016-08-25
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EP3259777B1 (en) 2021-04-28
CN107251218A (zh) 2017-10-13
ES2877771T3 (es) 2021-11-17
US20160240463A1 (en) 2016-08-18
US9691694B2 (en) 2017-06-27
KR102428876B1 (ko) 2022-08-02
BR112017017604B1 (pt) 2022-12-06
EP3259777A1 (en) 2017-12-27
KR20170118084A (ko) 2017-10-24

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