SG11201609805PA - Method for manufacturing soi wafer - Google Patents
Method for manufacturing soi waferInfo
- Publication number
- SG11201609805PA SG11201609805PA SG11201609805PA SG11201609805PA SG11201609805PA SG 11201609805P A SG11201609805P A SG 11201609805PA SG 11201609805P A SG11201609805P A SG 11201609805PA SG 11201609805P A SG11201609805P A SG 11201609805PA SG 11201609805P A SG11201609805P A SG 11201609805PA
- Authority
- SG
- Singapore
- Prior art keywords
- soi wafer
- manufacturing soi
- manufacturing
- wafer
- soi
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
- H01L21/67057—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing with the semiconductor substrates being dipped in baths or vessels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Weting (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014124046A JP6152829B2 (ja) | 2014-06-17 | 2014-06-17 | Soiウェーハの製造方法 |
PCT/JP2015/002042 WO2015194079A1 (fr) | 2014-06-17 | 2015-04-13 | Procédé de fabrication de plaquette soi |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201609805PA true SG11201609805PA (en) | 2016-12-29 |
Family
ID=54935098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201609805PA SG11201609805PA (en) | 2014-06-17 | 2015-04-13 | Method for manufacturing soi wafer |
Country Status (8)
Country | Link |
---|---|
US (1) | US9953860B2 (fr) |
EP (1) | EP3159911B1 (fr) |
JP (1) | JP6152829B2 (fr) |
KR (1) | KR102241303B1 (fr) |
CN (1) | CN106415784B (fr) |
SG (1) | SG11201609805PA (fr) |
TW (1) | TWI611568B (fr) |
WO (1) | WO2015194079A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021241044A1 (fr) | 2020-05-26 | 2021-12-02 | 信越半導体株式会社 | Procédé de fabrication d'une tranche de soi |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3319397B2 (ja) | 1998-07-07 | 2002-08-26 | 信越半導体株式会社 | 半導体製造装置およびこれを用いたエピタキシャルウェーハの製造方法 |
CN100454552C (zh) * | 2001-07-17 | 2009-01-21 | 信越半导体株式会社 | 贴合晶片的制造方法及贴合晶片、以及贴合soi晶片 |
JP4509488B2 (ja) * | 2003-04-02 | 2010-07-21 | 株式会社Sumco | 貼り合わせ基板の製造方法 |
JP2004349493A (ja) * | 2003-05-22 | 2004-12-09 | Canon Inc | 膜厚調整装置及びsoi基板の製造方法 |
JP2007266059A (ja) * | 2006-03-27 | 2007-10-11 | Sumco Corp | Simoxウェーハの製造方法 |
JP5415676B2 (ja) | 2007-05-30 | 2014-02-12 | 信越化学工業株式会社 | Soiウェーハの製造方法 |
JP2009054837A (ja) * | 2007-08-28 | 2009-03-12 | Sumco Corp | Simoxウェーハ製造方法およびsimoxウェーハ |
JP5320954B2 (ja) * | 2008-10-03 | 2013-10-23 | 信越半導体株式会社 | Soiウェーハの製造方法 |
-
2014
- 2014-06-17 JP JP2014124046A patent/JP6152829B2/ja active Active
-
2015
- 2015-04-13 WO PCT/JP2015/002042 patent/WO2015194079A1/fr active Application Filing
- 2015-04-13 CN CN201580027234.8A patent/CN106415784B/zh active Active
- 2015-04-13 KR KR1020167035257A patent/KR102241303B1/ko active IP Right Grant
- 2015-04-13 US US15/313,473 patent/US9953860B2/en active Active
- 2015-04-13 SG SG11201609805PA patent/SG11201609805PA/en unknown
- 2015-04-13 EP EP15809306.2A patent/EP3159911B1/fr active Active
- 2015-04-16 TW TW104112236A patent/TWI611568B/zh active
Also Published As
Publication number | Publication date |
---|---|
JP6152829B2 (ja) | 2017-06-28 |
TWI611568B (zh) | 2018-01-11 |
EP3159911B1 (fr) | 2021-06-09 |
US20170200634A1 (en) | 2017-07-13 |
WO2015194079A1 (fr) | 2015-12-23 |
EP3159911A4 (fr) | 2018-02-28 |
US9953860B2 (en) | 2018-04-24 |
KR20170018336A (ko) | 2017-02-17 |
EP3159911A1 (fr) | 2017-04-26 |
JP2016004890A (ja) | 2016-01-12 |
CN106415784B (zh) | 2019-06-07 |
TW201601296A (zh) | 2016-01-01 |
CN106415784A (zh) | 2017-02-15 |
KR102241303B1 (ko) | 2021-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG10201702358YA (en) | Wafer producing method | |
SG10201509454YA (en) | Wafer producing method | |
SG10201603903QA (en) | Wafer producing method | |
SG10201509475VA (en) | Wafer producing method | |
SG10201603714RA (en) | Wafer producing method | |
SG10201605092PA (en) | Wafer producing method | |
SG10201604080XA (en) | Wafer producing method | |
SG10201600557XA (en) | Wafer producing method | |
SG10201600555UA (en) | Wafer producing method | |
SG10201510273SA (en) | Wafer producing method | |
SG10201605424SA (en) | Wafer thinning method | |
SG10201600552YA (en) | Wafer producing method | |
SG10201510271QA (en) | Wafer producing method | |
SG10201601981YA (en) | Wafer producing method | |
SG10201605425VA (en) | Wafer thinning method | |
SG10201704123PA (en) | Wafer producing method | |
SG10201505185XA (en) | Wafer processing method | |
SG10201504351YA (en) | Wafer processing method | |
SG10201601975SA (en) | Wafer producing method | |
SG11201608562RA (en) | Method for manufacturing a bonded soi wafer | |
SG10201509471YA (en) | Wafer producing method | |
SG11201608563SA (en) | Method for manufacturing a bonded soi wafer and bonded soi wafer | |
SG10201610635SA (en) | Wafer production method | |
TWI800057B (zh) | 半導體裝置的製造方法 | |
SG11201801408YA (en) | Method for producing bonded soi wafer |