SG11201604539QA - Methods for uniform imprint pattern transfer of sub-20 nm features - Google Patents

Methods for uniform imprint pattern transfer of sub-20 nm features

Info

Publication number
SG11201604539QA
SG11201604539QA SG11201604539QA SG11201604539QA SG11201604539QA SG 11201604539Q A SG11201604539Q A SG 11201604539QA SG 11201604539Q A SG11201604539Q A SG 11201604539QA SG 11201604539Q A SG11201604539Q A SG 11201604539QA SG 11201604539Q A SG11201604539Q A SG 11201604539QA
Authority
SG
Singapore
Prior art keywords
sub
features
methods
pattern transfer
imprint pattern
Prior art date
Application number
SG11201604539QA
Other languages
English (en)
Inventor
Zhengmao Ye
Dwayne L Labrake
Original Assignee
Canon Nanotechnologies Inc
Molecular Imprints Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Nanotechnologies Inc, Molecular Imprints Inc filed Critical Canon Nanotechnologies Inc
Publication of SG11201604539QA publication Critical patent/SG11201604539QA/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
SG11201604539QA 2013-12-30 2014-12-30 Methods for uniform imprint pattern transfer of sub-20 nm features SG11201604539QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361921647P 2013-12-30 2013-12-30
PCT/US2014/072706 WO2015103232A1 (en) 2013-12-30 2014-12-30 Methods for uniform imprint pattern transfer of sub-20 nm features

Publications (1)

Publication Number Publication Date
SG11201604539QA true SG11201604539QA (en) 2016-07-28

Family

ID=52394376

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201604539QA SG11201604539QA (en) 2013-12-30 2014-12-30 Methods for uniform imprint pattern transfer of sub-20 nm features

Country Status (7)

Country Link
US (1) US9514950B2 (zh)
JP (1) JP6496320B2 (zh)
KR (1) KR102243630B1 (zh)
CN (1) CN106030406B (zh)
SG (1) SG11201604539QA (zh)
TW (1) TWI662359B (zh)
WO (1) WO2015103232A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10211051B2 (en) * 2015-11-13 2019-02-19 Canon Kabushiki Kaisha Method of reverse tone patterning
US10515847B2 (en) * 2017-09-29 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming vias and method for forming contacts in vias
CN108091552B (zh) * 2017-12-29 2021-03-02 长沙新材料产业研究院有限公司 一种在透光衬底上制备微纳米结构图案的方法
CN111542919B (zh) * 2018-01-05 2024-05-10 东京毅力科创株式会社 先进的接触孔图案化的方法
US10606171B2 (en) 2018-02-14 2020-03-31 Canon Kabushiki Kaisha Superstrate and a method of using the same
JP6960351B2 (ja) * 2018-02-19 2021-11-05 東京エレクトロン株式会社 処理方法
WO2019185110A1 (en) * 2018-03-26 2019-10-03 Applied Materials, Inc. Method for producing a multilevel imprint master, multilevel imprint master, and use of a multilevel imprint master
US10566194B2 (en) * 2018-05-07 2020-02-18 Lam Research Corporation Selective deposition of etch-stop layer for enhanced patterning
US10304744B1 (en) 2018-05-15 2019-05-28 International Business Machines Corporation Inverse tone direct print EUV lithography enabled by selective material deposition
US10615037B2 (en) * 2018-08-17 2020-04-07 International Business Machines Corporation Tone reversal during EUV pattern transfer using surface active layer assisted selective deposition
US11501969B2 (en) * 2019-01-22 2022-11-15 International Business Machines Corporation Direct extreme ultraviolet lithography on hard mask with reverse tone

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873087B1 (en) 1999-10-29 2005-03-29 Board Of Regents, The University Of Texas System High precision orientation alignment and gap control stages for imprint lithography processes
US6932934B2 (en) 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US6936194B2 (en) 2002-09-05 2005-08-30 Molecular Imprints, Inc. Functional patterning material for imprint lithography processes
US20040065252A1 (en) 2002-10-04 2004-04-08 Sreenivasan Sidlgata V. Method of forming a layer on a substrate to facilitate fabrication of metrology standards
US8349241B2 (en) 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
US7179396B2 (en) 2003-03-25 2007-02-20 Molecular Imprints, Inc. Positive tone bi-layer imprint lithography method
US7186656B2 (en) 2004-05-21 2007-03-06 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7396475B2 (en) * 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7157036B2 (en) 2003-06-17 2007-01-02 Molecular Imprints, Inc Method to reduce adhesion between a conformable region and a pattern of a mold
US8076386B2 (en) 2004-02-23 2011-12-13 Molecular Imprints, Inc. Materials for imprint lithography
KR101262730B1 (ko) * 2004-09-21 2013-05-09 몰레큘러 임프린츠 인코퍼레이티드 인-시츄 홈 구조 형성 방법
US7241395B2 (en) 2004-09-21 2007-07-10 Molecular Imprints, Inc. Reverse tone patterning on surfaces having planarity perturbations
US7205244B2 (en) * 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US20060144814A1 (en) * 2004-12-30 2006-07-06 Asml Netherlands B.V. Imprint lithography
US7256131B2 (en) * 2005-07-19 2007-08-14 Molecular Imprints, Inc. Method of controlling the critical dimension of structures formed on a substrate
US20070298176A1 (en) * 2006-06-26 2007-12-27 Dipietro Richard Anthony Aromatic vinyl ether based reverse-tone step and flash imprint lithography
JP5144127B2 (ja) * 2007-05-23 2013-02-13 キヤノン株式会社 ナノインプリント用のモールドの製造方法
JP5067848B2 (ja) * 2007-07-31 2012-11-07 キヤノン株式会社 パターンの形成方法
JP2009105252A (ja) * 2007-10-24 2009-05-14 Cheil Industries Inc 微細パターンの製造方法および光学素子
US20090166317A1 (en) * 2007-12-26 2009-07-02 Canon Kabushiki Kaisha Method of processing substrate by imprinting
JP5438959B2 (ja) * 2008-12-24 2014-03-12 東京応化工業株式会社 パターン形成方法
KR101680407B1 (ko) * 2009-08-17 2016-11-28 제이에스알 가부시끼가이샤 패턴 형성 방법
JP2011165855A (ja) * 2010-02-09 2011-08-25 Toshiba Corp パターン形成方法
NL2005992A (en) * 2010-03-22 2011-09-23 Asml Netherlands Bv Imprint lithography.
CN103091747B (zh) * 2011-10-28 2015-11-25 清华大学 一种光栅的制备方法
JP5818710B2 (ja) * 2012-02-10 2015-11-18 東京応化工業株式会社 パターン形成方法
JP2013172082A (ja) * 2012-02-22 2013-09-02 Toshiba Corp パターン形成方法、半導体装置の製造方法および塗布装置
US8802569B2 (en) * 2012-03-13 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor device

Also Published As

Publication number Publication date
KR102243630B1 (ko) 2021-04-23
US20150187590A1 (en) 2015-07-02
TW201531799A (zh) 2015-08-16
JP2017504201A (ja) 2017-02-02
TWI662359B (zh) 2019-06-11
KR20160103988A (ko) 2016-09-02
JP6496320B2 (ja) 2019-04-03
CN106030406A (zh) 2016-10-12
US9514950B2 (en) 2016-12-06
CN106030406B (zh) 2020-04-24
WO2015103232A1 (en) 2015-07-09

Similar Documents

Publication Publication Date Title
SG11201604539QA (en) Methods for uniform imprint pattern transfer of sub-20 nm features
EP2980831A4 (en) LAYERED FOIL FORMATION COMPOSITION FOR PRINTING AND STRUCTURAL FORMING METHOD
HK1221480A1 (zh) 印刷方法
SG11201600777WA (en) Method for producing dopaminergic neurons
HK1216183A1 (zh) 印刷多特性凹板特徵的方法
GB2515266B (en) Manufacturing Process for 3D Printed Objects
SG11201604509UA (en) Imprint lithography template and method for zero-gap imprinting
EP3087961A4 (en) METHOD FOR PRODUCING A VACUUMABLE ARTICLE
SG11201604407WA (en) Asymmetric template shape modulation for partial field imprinting
EP2998363A4 (en) PREPARATION FOR FINE ORGANIC PIGMENT
IL240272A (en) Tagging templates
EP2957543A4 (en) PROCESS FOR THE PREPARATION OF TRICHLOROSILANE
TWI560748B (en) Imprint apparatus and method of manufacturing article
TWI562273B (en) Holder, lithography apparatus, and method of manufacturing article
EP2980647A4 (en) METHOD FOR PRODUCING A FLEXODRUCK PLATE
EP2923818A4 (en) METHOD FOR PRODUCING A COATING FORM
EP2903007A4 (en) METHOD FOR PRODUCING A PATTERN
EP2975633A4 (en) METHOD FOR PRODUCING A PATTERN
SG11201510349TA (en) Embossing Material For Embossing Lithography
EP3073513A4 (en) Structure-manufacturing method using step-and-repeat imprinting technique
SG11201601432WA (en) Process for obtaining methionine
GB2512711B (en) Graphene production method
IL244310A0 (en) A method for producing rotogravure rolls
PL3089593T3 (pl) Zaawansowane formowanie gum do żucia
PL2842910T3 (pl) Sposób wytwarzania papieru grafenowego