SG11201501873QA - Method for manufacturing soi wafer - Google Patents

Method for manufacturing soi wafer

Info

Publication number
SG11201501873QA
SG11201501873QA SG11201501873QA SG11201501873QA SG11201501873QA SG 11201501873Q A SG11201501873Q A SG 11201501873QA SG 11201501873Q A SG11201501873Q A SG 11201501873QA SG 11201501873Q A SG11201501873Q A SG 11201501873QA SG 11201501873Q A SG11201501873Q A SG 11201501873QA
Authority
SG
Singapore
Prior art keywords
soi wafer
manufacturing soi
manufacturing
wafer
soi
Prior art date
Application number
SG11201501873QA
Other languages
English (en)
Inventor
Hiroji Aga
Toru Ishizuka
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201501873QA publication Critical patent/SG11201501873QA/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302Non-deposition formation processes
    • H10P14/6304Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302Non-deposition formation processes
    • H10P14/6322Formation by thermal treatments
SG11201501873QA 2012-11-21 2013-10-11 Method for manufacturing soi wafer SG11201501873QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012255719A JP5821828B2 (ja) 2012-11-21 2012-11-21 Soiウェーハの製造方法
PCT/JP2013/006072 WO2014080563A1 (ja) 2012-11-21 2013-10-11 Soiウェーハの製造方法

Publications (1)

Publication Number Publication Date
SG11201501873QA true SG11201501873QA (en) 2015-05-28

Family

ID=50775761

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201501873QA SG11201501873QA (en) 2012-11-21 2013-10-11 Method for manufacturing soi wafer

Country Status (7)

Country Link
US (1) US9378999B2 (https=)
EP (1) EP2924736B1 (https=)
JP (1) JP5821828B2 (https=)
KR (1) KR101910100B1 (https=)
CN (1) CN104620384B (https=)
SG (1) SG11201501873QA (https=)
WO (1) WO2014080563A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
JP6556511B2 (ja) * 2015-06-17 2019-08-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN110085549B (zh) * 2018-01-26 2021-06-04 沈阳硅基科技有限公司 一种双面注入得到soi的方法
CN110544668B (zh) 2018-05-28 2022-03-25 沈阳硅基科技有限公司 一种通过贴膜改变soi边缘stir的方法
CN109360805A (zh) * 2018-09-28 2019-02-19 沈阳硅基科技有限公司 一种图形soi硅片的制备方法
CN115188703B (zh) * 2022-05-16 2025-09-19 绍兴中芯集成电路制造股份有限公司 一种soi晶圆及制造方法
FR3146019A1 (fr) * 2023-02-16 2024-08-23 Soitec Procédé de formation d’une zone de fragisilation dans un substrat semi-conducteur

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355822A (ja) 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
JPH0680624B2 (ja) * 1990-02-28 1994-10-12 信越半導体株式会社 接合ウエーハの製造方法
JP3422225B2 (ja) * 1997-07-08 2003-06-30 三菱住友シリコン株式会社 貼り合わせ半導体基板及びその製造方法
JP3500063B2 (ja) * 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
FR2811807B1 (fr) 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
EP1667207B1 (en) * 2003-09-08 2019-07-17 SUMCO Corporation Bonded wafer and its manufacturing method
US20080315349A1 (en) * 2005-02-28 2008-12-25 Shin-Etsu Handotai Co., Ltd. Method for Manufacturing Bonded Wafer and Bonded Wafer
JP4398934B2 (ja) * 2005-02-28 2010-01-13 信越半導体株式会社 Soiウエーハの製造方法
US7902039B2 (en) 2006-11-30 2011-03-08 Sumco Corporation Method for manufacturing silicon wafer
JP5233111B2 (ja) 2006-11-30 2013-07-10 株式会社Sumco 貼り合わせsoiウェーハの製造方法
JP2011187502A (ja) * 2010-03-04 2011-09-22 Seiko Epson Corp 半導体装置の製造方法
CN102986020A (zh) * 2010-06-30 2013-03-20 康宁股份有限公司 对绝缘体基材上的硅进行精整的方法

Also Published As

Publication number Publication date
US20150243550A1 (en) 2015-08-27
EP2924736A1 (en) 2015-09-30
EP2924736B1 (en) 2017-08-30
KR20150087181A (ko) 2015-07-29
CN104620384B (zh) 2017-06-06
US9378999B2 (en) 2016-06-28
WO2014080563A1 (ja) 2014-05-30
JP5821828B2 (ja) 2015-11-24
EP2924736A4 (en) 2016-06-29
CN104620384A (zh) 2015-05-13
KR101910100B1 (ko) 2018-10-19
JP2014103329A (ja) 2014-06-05

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