SG11201403616WA - Method for manufacturing bonded soi wafer - Google Patents

Method for manufacturing bonded soi wafer

Info

Publication number
SG11201403616WA
SG11201403616WA SG11201403616WA SG11201403616WA SG11201403616WA SG 11201403616W A SG11201403616W A SG 11201403616WA SG 11201403616W A SG11201403616W A SG 11201403616WA SG 11201403616W A SG11201403616W A SG 11201403616WA SG 11201403616W A SG11201403616W A SG 11201403616WA
Authority
SG
Singapore
Prior art keywords
soi
layer surface
soi layer
treatment
rto
Prior art date
Application number
SG11201403616WA
Inventor
Norihiro Kobayashi
Toru Ishizuka
Hiroji Aga
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201403616WA publication Critical patent/SG11201403616WA/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

(i2) mwu ft iz s-5 iv x m £ titz s issaj n d9) mm IHMMi (43) m&'&m a 2013^8/3 1 0(01.08.2013) WIPOIPCT (10) WO 2013/111242 A1 (51) H01L 21/02 (2006.01) (21) (22) g&ttHQ: (25) (26) 4>§fl(£> s In: H01L 27/12 (2006.01) PCT/JP2012/008300 2012 ^ 12 M 26 0(26.12.2012) (30) fiBfefix — $: 2012-012256 2012 ^ 1 M 24 0(24.01.2012) JP (71) ttS H A: •(! Si ¥ # fa tt (SHIN-ETSU HAN- DOT AI CO., LTD.) [JP/JP]; T 1000004 T g 6 # 2 Tokyo (JP). (72) % BJ # : /h # ® <JA (KOBAYASHI, Norihiro); T 3790196 51^|5 2 Tl 1 3 # 1 fiiaJIigfa Gunma(JP). ES ^(ISHIZUKA, Toru); T3790196 rfT{l^[5 2 T g 1 3S1 BISPX ±§ Gunma (JP). P5J M ;i§ B] (AGA, Hiroji); T 3790196 51^|5 2 Tg 1 1 3 # fil$|5I±gfi Gunma (JP). (74) ftSA: iT'g ^ ^ (YOSHIMIYA, Mikio); T 1100005 Tg 6# 1 1-^-fg —F Tokyo (JP). (8i) (^ro&i^PBy, IS nj f b): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) *!£H (asrofci^isy > ±T(Dmm(Dfcm% II nlfb): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW), 3. — =j V 7 (AM, AZ, BY, KG, KZ, RU, TJ, TM), 3 — • V / ^ (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG). = (54) Title: BONDED WAFER SOI MANUFACTURING METHOD = (54)^BJC0^^ : O I ^ x —/ CJ •t CJ i-H o CJ = (A) i (B) 5 (C) g (D) ^ (E) (A) PREPARATION OF PEELED SOI WAFER (B) RTO TREATMENT (C) REMOVAL OF OXIDE FILM (D) THERMAL PLANARIZATION TREATMENT (E) SACRIFICIAL OXIDATION TREATMENT (57) Abstract: The present invention is a bonded SOI wafer manufacturing method characterized in that an RTO treat­ ment is applied to a peeled bonded SOI wafer which is ob­ tained by means of an ion injection peeing method, an oxide film formed on an SOI layer surface through the RTO treat­ ment is removed, then the SOI layer surface is planarized by applying thermal planarization a treatment that causes silicon atoms in the SOI layer surface migrate, and to a sacrificial ox­ idation treatment is subsequently applied in order to adjust the film thickness of the SOI layer. Provided as a result is a bonded SOI wafer manufacturing method that enables a high- quality SOI wafer, for which surface roughness of the SOI layer surface sufficiently is reduced, and deep pits on the SOI layer surface are reduced, to be efficiently manufactured. (57)^: U % bftfciJitf&CDlfiy-a'fr-fcbS O I ^i— MlCfcfL RTOM£fTl\ I^RTO^IIICcfcoTluIBS O I sir IBS O I Ji^SCDv'J =i u—->a >££i:£^&¥±IibtMfiiI£fToTflufBSO I Jia®£¥±HbU T flu IBs o i ztuc^y, so i Jia®a>a®ffi££+#ic'(£ IL, fro, SO I hjbM£3S£ titzm° W(Ds a o i Ji^-r&so i ^i-/\£ $$«fc<Sii-f6-<tjb<-e#6!£y^;b-fcj-so i WO 2013/111242 AlllllllH - (^^21^(3))
SG11201403616WA 2012-01-24 2012-12-26 Method for manufacturing bonded soi wafer SG11201403616WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012012256A JP5673572B2 (en) 2012-01-24 2012-01-24 Manufacturing method of bonded SOI wafer
PCT/JP2012/008300 WO2013111242A1 (en) 2012-01-24 2012-12-26 Bonded soi wafer manufacturing method

Publications (1)

Publication Number Publication Date
SG11201403616WA true SG11201403616WA (en) 2014-12-30

Family

ID=48873020

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201403616WA SG11201403616WA (en) 2012-01-24 2012-12-26 Method for manufacturing bonded soi wafer

Country Status (7)

Country Link
US (1) US9093497B2 (en)
EP (1) EP2808889B1 (en)
JP (1) JP5673572B2 (en)
KR (1) KR101846931B1 (en)
CN (1) CN104115255B (en)
SG (1) SG11201403616WA (en)
WO (1) WO2013111242A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016201454A (en) * 2015-04-09 2016-12-01 信越半導体株式会社 Soi wafer manufacturing method
CN104891430B (en) * 2015-04-17 2016-09-28 上海华虹宏力半导体制造有限公司 Wafer bonding method
JP6380245B2 (en) * 2015-06-15 2018-08-29 信越半導体株式会社 Manufacturing method of SOI wafer
CN106653677A (en) * 2016-09-22 2017-05-10 东莞市联洲知识产权运营管理有限公司 SOI wafer preparation method
JP6531743B2 (en) * 2016-09-27 2019-06-19 信越半導体株式会社 Method of manufacturing bonded SOI wafer
US11715639B2 (en) * 2016-11-29 2023-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabrication method therefor
CN106601615B (en) * 2016-12-27 2020-05-15 上海新傲科技股份有限公司 Annealing method for improving bonding strength
JP6834932B2 (en) * 2017-12-19 2021-02-24 株式会社Sumco Manufacturing method of support substrate for bonded wafer and manufacturing method of bonded wafer
CN110400773B (en) * 2018-04-24 2022-06-07 沈阳硅基科技有限公司 Method for preparing SOI silicon wafer by adopting rapid thermal treatment process
FR3132380A1 (en) * 2022-01-31 2023-08-04 Soitec Process for manufacturing a structure of the double semiconductor on insulator type

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (en) 1991-09-18 1993-10-29 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
JPH11307472A (en) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd Soi wafer and manufacture soi by hydrogen ion releasing method
JP2000124092A (en) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd Manufacture of soi wafer by hydrogen-ion implantation stripping method and soi wafer manufactured thereby
KR100874724B1 (en) * 2001-07-17 2008-12-19 신에쯔 한도타이 가부시키가이샤 Manufacturing method of bonded wafer
JP2004281805A (en) 2003-03-17 2004-10-07 Sumitomo Mitsubishi Silicon Corp Flattening process method for semiconductor wafer
JP2008526010A (en) 2004-12-28 2008-07-17 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ Method for obtaining thin layers with low hole density
JP4715470B2 (en) * 2005-11-28 2011-07-06 株式会社Ｓｕｍｃｏ Release wafer reclaim processing method and release wafer regenerated by this method
JP5125194B2 (en) * 2007-04-10 2013-01-23 信越半導体株式会社 Manufacturing method of bonded wafer
JP5135935B2 (en) 2007-07-27 2013-02-06 信越半導体株式会社 Manufacturing method of bonded wafer
JP2009289948A (en) * 2008-05-29 2009-12-10 Sumco Corp Laminated wafer manufacturing method

Also Published As

Publication number Publication date
CN104115255B (en) 2016-08-24
WO2013111242A1 (en) 2013-08-01
KR20140123505A (en) 2014-10-22
EP2808889A4 (en) 2015-09-30
CN104115255A (en) 2014-10-22
KR101846931B1 (en) 2018-04-10
JP5673572B2 (en) 2015-02-18
US9093497B2 (en) 2015-07-28
EP2808889B1 (en) 2016-10-26
JP2013153016A (en) 2013-08-08
US20150017783A1 (en) 2015-01-15
EP2808889A1 (en) 2014-12-03

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