SE8306663L - Forfarande for framstellning av halvledaranordning - Google Patents

Forfarande for framstellning av halvledaranordning

Info

Publication number
SE8306663L
SE8306663L SE8306663A SE8306663A SE8306663L SE 8306663 L SE8306663 L SE 8306663L SE 8306663 A SE8306663 A SE 8306663A SE 8306663 A SE8306663 A SE 8306663A SE 8306663 L SE8306663 L SE 8306663L
Authority
SE
Sweden
Prior art keywords
silicon
wafer
nickel
metallization
layer
Prior art date
Application number
SE8306663A
Other languages
English (en)
Swedish (sv)
Other versions
SE8306663D0 (sv
Inventor
A Nilarp
H J Gould
Original Assignee
Int Rectifier Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/447,760 external-priority patent/US4878099A/en
Application filed by Int Rectifier Corp filed Critical Int Rectifier Corp
Publication of SE8306663D0 publication Critical patent/SE8306663D0/xx
Publication of SE8306663L publication Critical patent/SE8306663L/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30608Anisotropic liquid etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Die Bonding (AREA)
SE8306663A 1982-12-08 1983-12-02 Forfarande for framstellning av halvledaranordning SE8306663L (sv)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44776182A 1982-12-08 1982-12-08
US06/447,760 US4878099A (en) 1982-12-08 1982-12-08 Metallizing system for semiconductor wafers

Publications (2)

Publication Number Publication Date
SE8306663D0 SE8306663D0 (sv) 1983-12-02
SE8306663L true SE8306663L (sv) 1984-06-09

Family

ID=27035081

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8306663A SE8306663L (sv) 1982-12-08 1983-12-02 Forfarande for framstellning av halvledaranordning

Country Status (5)

Country Link
DE (1) DE3344462A1 (xx)
FR (1) FR2537778B1 (xx)
GB (2) GB2132412B (xx)
IT (1) IT1194505B (xx)
SE (1) SE8306663L (xx)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3301666A1 (de) * 1983-01-20 1984-07-26 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren zur herstellung einer mehrschichtigen kontaktmetallisierung
JPH07118534B2 (ja) * 1990-02-22 1995-12-18 三菱電機株式会社 半導体装置の製造方法
US5422286A (en) * 1994-10-07 1995-06-06 United Microelectronics Corp. Process for fabricating high-voltage semiconductor power device
CN1241253C (zh) * 2002-06-24 2006-02-08 丰田合成株式会社 半导体元件的制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL135878C (xx) * 1961-08-12
US3288662A (en) * 1963-07-18 1966-11-29 Rca Corp Method of etching to dice a semiconductor slice
DE1258235B (de) * 1965-01-04 1968-01-04 Licentia Gmbh Verfahren zur Herstellung einer, die Sperrspannungsfestigkeit erhoehenden Randzonenprofilierung von Siliziumscheiben
DE1286641B (de) * 1966-08-26 1969-01-09 Bosch Gmbh Robert Verfahren zur Kontaktierung einer Halbleiteranordnung
DE1789062C3 (de) * 1968-09-30 1978-11-30 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen von Metallkontaktschichten für Halbleiteranordnungen
IT995593B (it) * 1972-12-11 1975-11-20 Rca Corp Dispositivo semiconduttore con connessioni a barretta e metodo di fabbricazione dello stesso
DE2332822B2 (de) * 1973-06-28 1978-04-27 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum Herstellen von diffundierten, kontaktierten und oberflächenpassivierten Halbleiterbauelementen aus Halbleiterscheiben aus Silizium
GB1487201A (en) * 1974-12-20 1977-09-28 Lucas Electrical Ltd Method of manufacturing semi-conductor devices
US4042951A (en) * 1975-09-25 1977-08-16 Texas Instruments Incorporated Gold-germanium alloy contacts for a semiconductor device
IN144812B (xx) * 1976-01-22 1978-07-15 Westinghouse Electric Corp
IT1059086B (it) * 1976-04-14 1982-05-31 Ates Componenti Elettron Procedimento per la passivazione di dispositivi a semiconduttore di potenza ad alta tensione inversa
DE2656015A1 (de) * 1976-12-10 1978-06-15 Bbc Brown Boveri & Cie Verfahren zum herstellen von halbleiterbauelementen
DE2709802A1 (de) * 1977-03-07 1978-09-14 Siemens Ag Verfahren zur entfernung von bei ionenimplantationsprozessen in halbleitersystemen entstehenden verunreinigungen
GB2064860B (en) * 1979-10-18 1984-01-25 Gen Electric Method for metallizing a semiconductor element
CA1164734A (en) * 1980-07-11 1984-04-03 Michael Schneider Method for applying an anti-reflection coating to a solar cell
US4339869A (en) * 1980-09-15 1982-07-20 General Electric Company Method of making low resistance contacts in semiconductor devices by ion induced silicides

Also Published As

Publication number Publication date
GB2132412A (en) 1984-07-04
DE3344462A1 (de) 1984-06-20
SE8306663D0 (sv) 1983-12-02
GB8529225D0 (en) 1986-01-02
GB2168843B (en) 1987-08-19
FR2537778B1 (fr) 1986-12-19
GB2168843A (en) 1986-06-25
GB8332808D0 (en) 1984-01-18
FR2537778A1 (fr) 1984-06-15
IT8324070A0 (it) 1983-12-06
IT1194505B (it) 1988-09-22
GB2132412B (en) 1987-08-19
DE3344462C2 (xx) 1989-12-28

Similar Documents

Publication Publication Date Title
US3290753A (en) Method of making semiconductor integrated circuit elements
CA1189748A (en) Maskless coating of metallurgical features of a dielectric substrate
KR970067579A (ko) 기판 지지 척에 대한 웨이퍼 스페이싱 마스크 및 제조 방법
US4638553A (en) Method of manufacture of semiconductor device
WO1990013143A1 (en) Metallized wafer-shaped substrate chip carriers
US3925880A (en) Semiconductor assembly with beam lead construction and method
US4965173A (en) Metallizing process and structure for semiconductor devices
SE8306663L (sv) Forfarande for framstellning av halvledaranordning
US3716765A (en) Semiconductor device with protective glass sealing
US4139434A (en) Method of making circuitry with bump contacts
US4878099A (en) Metallizing system for semiconductor wafers
EP0735576A3 (en) Integrated circuit fabrication
GB1100718A (en) Method of producing an electrical connection to a surface of an electronic device
EP0050512B1 (en) Method of forming electrical interconnections on contact pads of semi-conductor devices
KR930008994A (ko) 웨이퍼 결합 기술
JPH01302740A (ja) 誘電体分離半導体基板およびその製造方法
JPH03198342A (ja) 半導体装置の製造方法
KR0119275B1 (ko) 기판접합기술을 이용한 서로 다른 활성층 두께를 갖는 soi구조의 기판 제조방법
JP2576462B2 (ja) 半導体装置の製造方法
JPS61260648A (ja) 半導体装置の実装方法
FR2449332A1 (fr) Methode de protection de zones de contact sur des dispositifs a semi-conducteurs
JPS63202034A (ja) 半導体装置の製造方法
EP0155311A1 (en) REPAIR METHOD FOR BURNED CONTACTS IN MOSFET ARRANGEMENTS.
JPH0194640A (ja) 半導体装置およびその製造方法
JPH03149850A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
NAV Patent application has lapsed

Ref document number: 8306663-9

Effective date: 19900329

Format of ref document f/p: F