SE501190C2 - Digitalt styrd kristalloscillator - Google Patents

Digitalt styrd kristalloscillator

Info

Publication number
SE501190C2
SE501190C2 SE9301435A SE9301435A SE501190C2 SE 501190 C2 SE501190 C2 SE 501190C2 SE 9301435 A SE9301435 A SE 9301435A SE 9301435 A SE9301435 A SE 9301435A SE 501190 C2 SE501190 C2 SE 501190C2
Authority
SE
Sweden
Prior art keywords
delay line
phase
delay
oscillator
active
Prior art date
Application number
SE9301435A
Other languages
English (en)
Swedish (sv)
Other versions
SE9301435D0 (sv
SE9301435L (sv
Inventor
Per Liedberg
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE9301435A priority Critical patent/SE501190C2/sv
Publication of SE9301435D0 publication Critical patent/SE9301435D0/xx
Priority to ES94914649T priority patent/ES2129638T3/es
Priority to BR9406334A priority patent/BR9406334A/pt
Priority to EP94914649A priority patent/EP0700600B1/en
Priority to DK94914649T priority patent/DK0700600T3/da
Priority to CN94191897A priority patent/CN1035352C/zh
Priority to PCT/SE1994/000268 priority patent/WO1994026032A1/en
Priority to DE69416586T priority patent/DE69416586T2/de
Priority to AU66927/94A priority patent/AU677662B2/en
Priority to JP52414594A priority patent/JP3255418B2/ja
Priority to CA002159189A priority patent/CA2159189A1/en
Priority to KR1019950704737A priority patent/KR100233024B1/ko
Priority to US08/234,109 priority patent/US5550514A/en
Publication of SE9301435L publication Critical patent/SE9301435L/xx
Publication of SE501190C2 publication Critical patent/SE501190C2/sv
Priority to NO954230A priority patent/NO310090B1/no
Priority to FI955138A priority patent/FI955138A/fi
Priority to GR990401310T priority patent/GR3030223T3/el

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Circuits Of Receivers In General (AREA)
  • Pulse Circuits (AREA)
SE9301435A 1993-04-28 1993-04-28 Digitalt styrd kristalloscillator SE501190C2 (sv)

Priority Applications (16)

Application Number Priority Date Filing Date Title
SE9301435A SE501190C2 (sv) 1993-04-28 1993-04-28 Digitalt styrd kristalloscillator
KR1019950704737A KR100233024B1 (ko) 1993-04-28 1994-03-24 기준주파수의 위상에 안정된 로컬주파수 발전기로부터의 위상을 정렬하는 방법 및 장치
AU66927/94A AU677662B2 (en) 1993-04-28 1994-03-24 Digital controlled XTAL OSC
CA002159189A CA2159189A1 (en) 1993-04-28 1994-03-24 Digital controlled xtal osc
EP94914649A EP0700600B1 (en) 1993-04-28 1994-03-24 Digital controlled crystal oscillator
DK94914649T DK0700600T3 (da) 1993-04-28 1994-03-24 Digital styret krystaloscillator
CN94191897A CN1035352C (zh) 1993-04-28 1994-03-24 数字受控晶体振荡器
PCT/SE1994/000268 WO1994026032A1 (en) 1993-04-28 1994-03-24 Digital controlled xtal osc
DE69416586T DE69416586T2 (de) 1993-04-28 1994-03-24 Digital gesteuerter quarzoszillator
ES94914649T ES2129638T3 (es) 1993-04-28 1994-03-24 Oscilador de cristal de cuarzo controlado numericamente.
JP52414594A JP3255418B2 (ja) 1993-04-28 1994-03-24 ディジタル制御の水晶発振器
BR9406334A BR9406334A (pt) 1993-04-28 1994-03-24 Processo e dispositivo para alinhar a fase de um oscilador de frequência local estável
US08/234,109 US5550514A (en) 1993-04-28 1994-04-28 Digital controlled xtal osc
NO954230A NO310090B1 (no) 1993-04-28 1995-10-23 Digitalt styrt krystall-oscillator
FI955138A FI955138A (fi) 1993-04-28 1995-10-27 Digitaalinen ohjattu kideoskillaattori
GR990401310T GR3030223T3 (en) 1993-04-28 1999-05-14 Digital controlled xtal osc

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9301435A SE501190C2 (sv) 1993-04-28 1993-04-28 Digitalt styrd kristalloscillator

Publications (3)

Publication Number Publication Date
SE9301435D0 SE9301435D0 (sv) 1993-04-28
SE9301435L SE9301435L (sv) 1994-10-29
SE501190C2 true SE501190C2 (sv) 1994-12-05

Family

ID=20389747

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9301435A SE501190C2 (sv) 1993-04-28 1993-04-28 Digitalt styrd kristalloscillator

Country Status (16)

Country Link
US (1) US5550514A (da)
EP (1) EP0700600B1 (da)
JP (1) JP3255418B2 (da)
KR (1) KR100233024B1 (da)
CN (1) CN1035352C (da)
AU (1) AU677662B2 (da)
BR (1) BR9406334A (da)
CA (1) CA2159189A1 (da)
DE (1) DE69416586T2 (da)
DK (1) DK0700600T3 (da)
ES (1) ES2129638T3 (da)
FI (1) FI955138A (da)
GR (1) GR3030223T3 (da)
NO (1) NO310090B1 (da)
SE (1) SE501190C2 (da)
WO (1) WO1994026032A1 (da)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5666079A (en) * 1994-05-06 1997-09-09 Plx Technology, Inc. Binary relative delay line
DE4427972C1 (de) * 1994-08-08 1995-07-27 Siemens Ag Integrierbare Taktrückgewinnungsschaltung
JP3355894B2 (ja) * 1995-09-27 2002-12-09 安藤電気株式会社 可変遅延回路
GB9704719D0 (en) * 1997-03-07 1997-04-23 Plessey Semiconductors Ltd Frequency tracking arrangements
DE19714494C1 (de) * 1997-04-08 1998-10-01 Siemens Ag Verfahren und Vorrichtung zum Synchronisieren eines Taktgenerators
US6084933A (en) * 1997-11-17 2000-07-04 Advanced Micro Devices, Inc. Chip operating conditions compensated clock generation
US5939916A (en) * 1997-12-23 1999-08-17 Northern Telecom Limited Phase shifter suitable for clock recovery systems
JP3789222B2 (ja) * 1998-01-16 2006-06-21 富士通株式会社 Ｄｌｌ回路及びそれを内蔵するメモリデバイス
US6522188B1 (en) 1998-04-10 2003-02-18 Top Layer Networks, Inc. High-speed data bus for network switching
JP2001075671A (ja) * 1999-09-08 2001-03-23 Nec Corp 位相補償回路
US6204709B1 (en) * 1999-09-30 2001-03-20 Nortel Networks Limited Unlimited phase tracking delay locked loop
KR100574927B1 (ko) * 1999-10-29 2006-05-02 삼성전자주식회사 듀얼 위상검출기
JP4060514B2 (ja) * 2000-05-22 2008-03-12 株式会社東芝 同期信号発生回路
DE10029421C2 (de) 2000-06-15 2002-07-11 Infineon Technologies Ag Kalibriervorrichtung und -verfahren für die Taktgenerierung auf einem integrierten Schaltkreis
US6518812B1 (en) * 2000-07-20 2003-02-11 Silicon Graphics, Inc. Discrete delay line system and method
US6424197B1 (en) * 2000-10-24 2002-07-23 Exar Corporation Rising and falling edge aperture delay control circuit in analog front end of imaging system
US6819726B2 (en) * 2000-12-07 2004-11-16 International Business Machines Corporation Dynamic phase alignment circuit
DE10064929A1 (de) * 2000-12-23 2002-07-04 Alcatel Sa Verfahren und Kompensationsmodul zur Phasenkompensation von Taktsignalen
JP3478284B2 (ja) * 2001-08-10 2003-12-15 ソニー株式会社 半導体装置
KR20030037591A (ko) * 2001-11-06 2003-05-14 삼성전자주식회사 넓은 동기 범위를 가지는 적응형 지연동기루프
US7333527B2 (en) * 2001-11-27 2008-02-19 Sun Microsystems, Inc. EMI reduction using tunable delay lines
FR2844655A1 (fr) * 2002-09-13 2004-03-19 St Microelectronics Sa Transformation d'un signal periodique en un signal de frequence ajustable
US6710636B1 (en) * 2002-10-03 2004-03-23 Cypress Semiconductor Corporation Method and system for high resolution delay lock loop
US6980041B2 (en) * 2002-10-04 2005-12-27 Hewlett-Packard Development Company, L.P. Non-iterative introduction of phase delay into signal without feedback
US6977538B2 (en) * 2002-10-18 2005-12-20 Agilent Technologies, Inc. Delay unit for periodic signals
DE10330796B4 (de) * 2002-10-30 2023-09-14 Hynix Semiconductor Inc. Registergesteuerter Delay Locked Loop mit Beschleunigungsmodus
FR2854293B1 (fr) * 2003-04-25 2005-07-22 St Microelectronics Sa Dispositif de reception de donnees serie
JP2005049970A (ja) 2003-07-30 2005-02-24 Renesas Technology Corp 半導体集積回路
JP4102864B2 (ja) * 2004-07-23 2008-06-18 テクトロニクス・インターナショナル・セールス・ゲーエムベーハー 遅延可変回路
KR100713082B1 (ko) * 2005-03-02 2007-05-02 주식회사 하이닉스반도체 클럭의 듀티 비율을 조정할 수 있는 지연 고정 루프
US7190202B1 (en) * 2005-04-05 2007-03-13 Xilink, Inc. Trim unit having less jitter
US7332950B2 (en) * 2005-06-14 2008-02-19 Micron Technology, Inc. DLL measure initialization circuit for high frequency operation
CN1960183B (zh) * 2005-10-31 2010-07-28 盛群半导体股份有限公司 自动调整的高准确性振荡器
DE112007000758B4 (de) 2006-03-31 2011-04-14 Anritsu Corp., Atsugi-shi Datensignal-Erzeugungsvorrichtung #
US7405604B2 (en) * 2006-04-20 2008-07-29 Realtek Semiconductor Corp. Variable delay clock circuit and method thereof
JP5088941B2 (ja) * 2006-08-10 2012-12-05 パナソニック株式会社 可変遅延装置
US8954017B2 (en) 2011-08-17 2015-02-10 Broadcom Corporation Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device
US9106400B2 (en) * 2012-10-23 2015-08-11 Futurewei Technologies, Inc. Hybrid timing recovery for burst mode receiver in passive optical networks
CN103065172B (zh) * 2012-12-26 2015-09-16 广州中大微电子有限公司 一种rfid读写器的接收端电路及其实现方法
US9395745B2 (en) * 2014-02-10 2016-07-19 Analog Devices, Inc. Redundant clock switchover
DE102015101745B4 (de) * 2014-02-10 2016-12-08 Analog Devices, Inc. Redundante takt-umschaltung
CN107872221B (zh) * 2016-09-26 2021-04-27 深圳市中兴微电子技术有限公司 一种全相位数字延迟锁相环装置及工作方法
CN108075770B (zh) * 2016-11-15 2024-04-16 无锡中微爱芯电子有限公司 一种数字延迟锁定环
CN112485519A (zh) * 2020-12-03 2021-03-12 成都市精准时空科技有限公司 一种基于延迟线的绝对频差测量方法及系统及装置及介质
US11775002B2 (en) 2021-07-27 2023-10-03 International Business Machines Corporation Redundant clock switch

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4119796A (en) * 1976-11-01 1978-10-10 Versitron, Inc. Automatic data synchronizer
JPS6083166A (ja) * 1983-10-14 1985-05-11 Hitachi Ltd 半導体集積回路装置
DE3481472D1 (de) * 1984-12-21 1990-04-05 Ibm Digitale phasenregelschleife.
JPS6270922A (ja) * 1985-09-04 1987-04-01 Fujitsu Ltd クロツク位相調整方式
US4795985A (en) * 1986-04-01 1989-01-03 Hewlett-Packard Company Digital phase lock loop
US4796095A (en) * 1986-09-09 1989-01-03 Rioch Company, Limited Method of generating image scanning clock signals in optical scanning apparatus
US4868514A (en) * 1987-11-17 1989-09-19 International Business Machines Corporation Apparatus and method for digital compensation of oscillator drift
JP2629028B2 (ja) * 1988-08-10 1997-07-09 株式会社日立製作所 クロック信号供給方法および装置
JPH0292021A (ja) * 1988-09-29 1990-03-30 Mitsubishi Rayon Co Ltd ディジタルｐｌｌ回路
JPH0396015A (ja) * 1989-09-08 1991-04-22 Oki Electric Ind Co Ltd 高速デジタルｐｌｌ装置
CA2001266C (en) * 1989-10-23 1996-08-06 John Robert Long Digital phase aligner and method for its operation
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
US5079519A (en) * 1991-02-14 1992-01-07 Notorola, Inc. Digital phase lock loop for a gate array
JPH04373009A (ja) * 1991-06-21 1992-12-25 Hitachi Ltd クロック信号の位相調整方法及び電子装置
US5281874A (en) * 1992-02-14 1994-01-25 Vlsi Technology, Inc. Compensated digital delay semiconductor device with selectable output taps and method therefor

Also Published As

Publication number Publication date
GR3030223T3 (en) 1999-08-31
CN1035352C (zh) 1997-07-02
CA2159189A1 (en) 1994-11-10
NO954230L (no) 1995-12-08
SE9301435D0 (sv) 1993-04-28
JP3255418B2 (ja) 2002-02-12
CN1121753A (zh) 1996-05-01
US5550514A (en) 1996-08-27
FI955138A0 (fi) 1995-10-27
NO954230D0 (no) 1995-10-23
DE69416586D1 (de) 1999-03-25
SE9301435L (sv) 1994-10-29
KR960702216A (ko) 1996-03-28
DK0700600T3 (da) 1999-05-10
AU677662B2 (en) 1997-05-01
EP0700600A1 (en) 1996-03-13
DE69416586T2 (de) 1999-06-24
AU6692794A (en) 1994-11-21
FI955138A (fi) 1995-10-27
BR9406334A (pt) 1995-12-26
EP0700600B1 (en) 1999-02-17
JPH08509584A (ja) 1996-10-08
ES2129638T3 (es) 1999-06-16
KR100233024B1 (ko) 1999-12-01
NO310090B1 (no) 2001-05-14
WO1994026032A1 (en) 1994-11-10

Similar Documents

Publication Publication Date Title
SE501190C2 (sv) Digitalt styrd kristalloscillator
US5451894A (en) Digital full range rotating phase shifter
EP0010077B1 (en) A method of and an arrangement for regulating the phase position of a controlled signal in relation to a reference signal in a telecommunication system
EP2073389B1 (en) Method and apparatus for multi-mode clock data recovery
US4805195A (en) Selectable timing delay circuit
US3882412A (en) Drift compensated phase lock loop
US5844436A (en) Method of recovering a sampling clock in a framed data communications format with reduced phase jitter and wander
US5302916A (en) Wide range digital frequency detector
US4181975A (en) Digital delay line apparatus
EP0576168B1 (en) Digital phase locked loop
SE501385C2 (sv) Krets för bibehållande av en klocksignal
EP0116559A1 (en) TIMING EQUALIZATION CIRCUIT.
US3024417A (en) Proportional digital synchronizer
EP2546991A1 (en) Clock generation circuit
EP1087563B1 (en) System and method for reliably switching between redundant clocks
US5003308A (en) Serial data receiver with phase shift detection
US6313708B1 (en) Analog phase locked loop holdover
SE502901C2 (sv) Digital faskomparator
EP0236419B1 (en) Phase changer
GB2052815A (en) Digital frequency multiplier
US5533073A (en) Method and an arrangement for minimizing a phase difference between two datastreams prior to changeover
JP2016019283A (ja) 位相調整を使用して発振器出力周波数をコントロールするためのシステム及び技術
GB2282719A (en) Digitally controlled phase locked loop
EP0966103B1 (en) Frequency synthesiser
SU582574A1 (ru) Устройство фазовой подстройки частоты

Legal Events

Date Code Title Description
NUG Patent has lapsed