SE449672B - Minnesanordning, innefattande tva par atkomstledningar - Google Patents

Minnesanordning, innefattande tva par atkomstledningar

Info

Publication number
SE449672B
SE449672B SE8202234A SE8202234A SE449672B SE 449672 B SE449672 B SE 449672B SE 8202234 A SE8202234 A SE 8202234A SE 8202234 A SE8202234 A SE 8202234A SE 449672 B SE449672 B SE 449672B
Authority
SE
Sweden
Prior art keywords
pair
access
elements
charge
lines
Prior art date
Application number
SE8202234A
Other languages
English (en)
Swedish (sv)
Other versions
SE8202234L (sv
Inventor
B S Moffitt
A R Ross
Eatontown Nj
Allentown Penn
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of SE8202234L publication Critical patent/SE8202234L/
Publication of SE449672B publication Critical patent/SE449672B/sv

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
SE8202234A 1981-04-23 1982-04-07 Minnesanordning, innefattande tva par atkomstledningar SE449672B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/256,697 US4395765A (en) 1981-04-23 1981-04-23 Multiport memory array

Publications (2)

Publication Number Publication Date
SE8202234L SE8202234L (sv) 1982-10-24
SE449672B true SE449672B (sv) 1987-05-11

Family

ID=22973231

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8202234A SE449672B (sv) 1981-04-23 1982-04-07 Minnesanordning, innefattande tva par atkomstledningar

Country Status (16)

Country Link
US (1) US4395765A (fr)
JP (1) JPS57181493A (fr)
AU (1) AU546325B2 (fr)
BE (1) BE892929A (fr)
CA (1) CA1173566A (fr)
CH (1) CH654947A5 (fr)
DE (1) DE3214230C2 (fr)
ES (1) ES8302945A1 (fr)
FR (1) FR2504714B1 (fr)
GB (1) GB2097623B (fr)
HK (1) HK7086A (fr)
IE (1) IE53486B1 (fr)
IL (1) IL65529A (fr)
IT (1) IT1150876B (fr)
NL (1) NL192755C (fr)
SE (1) SE449672B (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
US4737933A (en) * 1983-02-22 1988-04-12 Storage Technology Partners CMOS multiport general purpose register
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
FR2595859B1 (fr) * 1986-03-14 1988-05-13 Radiotechnique Compelec Memoire avec tampon amplificateur
DE3881222D1 (de) * 1987-01-23 1993-07-01 Siemens Ag Halbleiterspeicher mit wahlfreiem zugriff ueber zwei getrennte ein/ausgaenge.
JPS63225836A (ja) * 1987-03-13 1988-09-20 Brother Ind Ltd 記憶装置
US5093807A (en) * 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
US5166903A (en) * 1988-10-25 1992-11-24 International Business Machines Corporation Memory organization with arrays having an alternate data port facility
US5150328A (en) * 1988-10-25 1992-09-22 Internation Business Machines Corporation Memory organization with arrays having an alternate data port facility
US4995001A (en) * 1988-10-31 1991-02-19 International Business Machines Corporation Memory cell and read circuit
US5235543A (en) * 1989-12-29 1993-08-10 Intel Corporation Dual port static memory with one cycle read-modify-write
US5708850A (en) * 1994-07-27 1998-01-13 Sony Corporation Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3618050A (en) * 1969-05-07 1971-11-02 Teletype Corp Read-only memory arrays in which a portion of the memory-addressing circuitry is integral to the array
US3636528A (en) * 1969-11-14 1972-01-18 Shell Oil Co Half-bit memory cell array with nondestructive readout
US3866180A (en) * 1973-04-02 1975-02-11 Amdahl Corp Having an instruction pipeline for concurrently processing a plurality of instructions
US3916394A (en) * 1974-12-09 1975-10-28 Honeywell Inf Systems High-speed random access memory
US3978459A (en) * 1975-04-21 1976-08-31 Intel Corporation High density mos memory array
US4051358A (en) * 1976-02-20 1977-09-27 Intel Corporation Apparatus and method for composing digital information on a data bus
JPS52129337A (en) * 1976-04-23 1977-10-29 Hitachi Ltd Memory circuit
US4104719A (en) * 1976-05-20 1978-08-01 The United States Of America As Represented By The Secretary Of The Navy Multi-access memory module for data processing systems
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
US4123799A (en) * 1977-09-19 1978-10-31 Motorola, Inc. High speed IFGET sense amplifier/latch
US4209851A (en) * 1978-07-19 1980-06-24 Texas Instruments Incorporated Semiconductor memory cell with clocked voltage supply from data lines
EP0011375A1 (fr) * 1978-11-17 1980-05-28 Motorola, Inc. Circuit de mémoire à accès aléatoire et portes d'accès multiples pour registre de traitement de l'information
JPS5634179A (en) * 1979-08-24 1981-04-06 Mitsubishi Electric Corp Control circuit for memory unit

Also Published As

Publication number Publication date
IE820949L (en) 1982-10-23
US4395765A (en) 1983-07-26
CH654947A5 (de) 1986-03-14
AU8293282A (en) 1982-10-28
IL65529A (en) 1985-05-31
DE3214230A1 (de) 1982-11-18
IE53486B1 (en) 1988-11-23
GB2097623A (en) 1982-11-03
NL192755C (nl) 1998-01-06
FR2504714A1 (fr) 1982-10-29
AU546325B2 (en) 1985-08-29
NL8201680A (nl) 1982-11-16
GB2097623B (en) 1984-09-26
CA1173566A (fr) 1984-08-28
IL65529A0 (en) 1982-07-30
NL192755B (nl) 1997-09-01
DE3214230C2 (de) 1994-01-13
IT1150876B (it) 1986-12-17
JPS57181493A (en) 1982-11-08
BE892929A (fr) 1982-08-16
ES511598A0 (es) 1983-02-16
FR2504714B1 (fr) 1989-04-28
IT8220885A0 (it) 1982-04-22
SE8202234L (sv) 1982-10-24
ES8302945A1 (es) 1983-02-16
HK7086A (en) 1986-02-07

Similar Documents

Publication Publication Date Title
KR940000148B1 (ko) 듀얼포트 반도체 기억장치
US5345419A (en) Fifo with word line match circuits for flag generation
JP2740063B2 (ja) 半導体記憶装置
US4875196A (en) Method of operating data buffer apparatus
US6856527B1 (en) Multi-compare content addressable memory cell
KR950010758B1 (ko) 다이나믹형 메모리
EP0918335A2 (fr) Mémoire associative
SE449672B (sv) Minnesanordning, innefattande tva par atkomstledningar
US5544101A (en) Memory device having a latching multiplexer and a multiplexer block therefor
JPH0760594B2 (ja) 半導体記憶装置
US5036494A (en) Memory accessing
US6175533B1 (en) Multi-port memory cell with preset
GB1519985A (en) Computer momories
US20010043506A1 (en) Random access memory having independent read port and write port and process for writing to and reading from the same
EP0575829B1 (fr) Mémoire à accès séquentiel avec compteur et pointeurs d'addresses de colonnes
EP1137011B1 (fr) Mémoire non-volatile à structure NOR programmable par séquences de mots
EP0570977A2 (fr) Dispositif de mémoire à semi-conducteur
US5014244A (en) Integrated memory circuit with parallel and serial input and output
US4020470A (en) Simultaneous addressing of different locations in a storage unit
US5524226A (en) Register file system for microcomputer including a decoding system for concurrently activating source and destination word lines
JPS6052999A (ja) メモリ装置
US4677591A (en) Semiconductor memory device
EP1271548B1 (fr) Mémoire adressable par le contenu avec circuit de combinaison pour signaux de correspondance à portes AND
US5394364A (en) High-speed memory readout circuit using a single set of data buffers
US6304103B1 (en) FPGA using RAM control signal lines as routing or logic resources after configuration

Legal Events

Date Code Title Description
NUG Patent has lapsed

Ref document number: 8202234-4

Effective date: 19900411

Format of ref document f/p: F