SE377003C - Integrerad krets med halvledarskikt pa elektriskt isolerande substrat och med metalliska ledningsbanor med kontaktanslutningar och sett for tillverkning av densamma - Google Patents
Integrerad krets med halvledarskikt pa elektriskt isolerande substrat och med metalliska ledningsbanor med kontaktanslutningar och sett for tillverkning av densammaInfo
- Publication number
- SE377003C SE377003C SE7302222A SE7302222A SE377003C SE 377003 C SE377003 C SE 377003C SE 7302222 A SE7302222 A SE 7302222A SE 7302222 A SE7302222 A SE 7302222A SE 377003 C SE377003 C SE 377003C
- Authority
- SE
- Sweden
- Prior art keywords
- integrated circuit
- kits
- insulating substrate
- manufacture
- semiconductor layer
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000011810 insulating material Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19722207510 DE2207510C3 (de) | 1972-02-17 | Verfahren zur Herstellung integrierter Schaltungen mit Halbleiterschichten auf isolierendem Substrat |
Publications (2)
Publication Number | Publication Date |
---|---|
SE377003B SE377003B (sv) | 1975-06-16 |
SE377003C true SE377003C (sv) | 1976-12-20 |
Family
ID=5836253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE7302222A SE377003C (sv) | 1972-02-17 | 1973-02-16 | Integrerad krets med halvledarskikt pa elektriskt isolerande substrat och med metalliska ledningsbanor med kontaktanslutningar och sett for tillverkning av densamma |
Country Status (11)
Country | Link |
---|---|
US (1) | US4017769A (sv) |
JP (1) | JPS4893962A (sv) |
AT (1) | AT339372B (sv) |
BE (1) | BE795556A (sv) |
CH (1) | CH551695A (sv) |
FR (1) | FR2172200B1 (sv) |
GB (1) | GB1367420A (sv) |
IT (1) | IT979053B (sv) |
LU (1) | LU67043A1 (sv) |
NL (1) | NL7302015A (sv) |
SE (1) | SE377003C (sv) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5047580A (sv) * | 1973-08-28 | 1975-04-28 | ||
US4262299A (en) * | 1979-01-29 | 1981-04-14 | Rca Corporation | Semiconductor-on-insulator device and method for its manufacture |
JPS5846174B2 (ja) * | 1981-03-03 | 1983-10-14 | 株式会社東芝 | 半導体集積回路 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1160744A (en) * | 1965-11-05 | 1969-08-06 | Plessey Co Ltd | Improvements in or relating to Semiconductor Devices |
US3413145A (en) * | 1965-11-29 | 1968-11-26 | Rca Corp | Method of forming a crystalline semiconductor layer on an alumina substrate |
US3736193A (en) * | 1970-10-26 | 1973-05-29 | Fairchild Camera Instr Co | Single crystal-polycrystalline process for electrical isolation in integrated circuits |
-
0
- BE BE795556D patent/BE795556A/xx unknown
-
1972
- 1972-12-05 AT AT1035072A patent/AT339372B/de not_active IP Right Cessation
- 1972-12-05 CH CH1770072A patent/CH551695A/xx not_active IP Right Cessation
- 1972-12-12 GB GB5729972A patent/GB1367420A/en not_active Expired
-
1973
- 1973-02-13 NL NL7302015A patent/NL7302015A/xx not_active Application Discontinuation
- 1973-02-13 IT IT20320/73A patent/IT979053B/it active
- 1973-02-14 FR FR7305135A patent/FR2172200B1/fr not_active Expired
- 1973-02-15 LU LU67043A patent/LU67043A1/xx unknown
- 1973-02-16 JP JP48019164A patent/JPS4893962A/ja active Pending
- 1973-02-16 US US05/333,334 patent/US4017769A/en not_active Expired - Lifetime
- 1973-02-16 SE SE7302222A patent/SE377003C/sv unknown
Also Published As
Publication number | Publication date |
---|---|
IT979053B (it) | 1974-09-30 |
DE2207510A1 (de) | 1973-08-30 |
SE377003B (sv) | 1975-06-16 |
FR2172200A1 (sv) | 1973-09-28 |
GB1367420A (en) | 1974-09-18 |
LU67043A1 (sv) | 1973-04-19 |
NL7302015A (sv) | 1973-08-21 |
US4017769A (en) | 1977-04-12 |
CH551695A (de) | 1974-07-15 |
BE795556A (fr) | 1973-06-18 |
DE2207510B2 (de) | 1974-10-24 |
FR2172200B1 (sv) | 1978-04-14 |
ATA1035072A (de) | 1977-02-15 |
AT339372B (de) | 1977-10-10 |
JPS4893962A (sv) | 1973-12-04 |
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