RU2812687C1 - Logical module - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: logic module is designed to implement any of the simple symmetrical Boolean functions depending on five arguments - input binary signals, and can be used in digital computer systems as a means of converting codes. The logic module comprises two AND gates (1₁, 1₂), three EXCLUSIVE OR gates (2₁, 2₂, 2₃) and four majority gates (3₁, 3₂, 3₃, 3₄).

EFFECT: simplifying the logic module circuit by reducing its Quain price while maintaining functionality.

1 cl, 1 dwg, 1 tbl

Description

The invention relates to computer technology and can be used in the construction of automation equipment, functional units of control systems, etc.

There are known logical modules (see, for example, [1]) that contain logical elements and, using a constant setting, implement any of four simple symmetric Boolean functions that depend on four arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using known logical modules is limited functionality due to the fact that the implementation of any of the five simple symmetrical Boolean functions, which depend on five arguments - input binary signals, is not performed.

The closest device of the same purpose to the claimed invention in terms of the set of characteristics is the logical module [2] adopted as a prototype, which contains logical elements and, using a constant setting, implements any of five simple symmetrical Boolean functions, depending on five arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using the prototype is the circuit complexity due to the fact that the Quine price of the prototype circuit is 28.

The technical result of the invention is to simplify the logic module circuit by reducing its cost according to Quine while maintaining the functionality of the prototype.

The specified technical result when implementing the invention is achieved by the fact that in a logical module containing two elements and four majority elements, the first input of the second and the output of the fourth majority elements are connected, respectively, to the first configuration input and output of the logical module, the peculiarity is that it three exclusive OR elements are introduced, i -th ( ) input j -th ( ) of the majority element and the first, second inputs of the first AND element are connected, respectively, to the i -th input of the j -th and the first, second inputs of the third exclusive OR elements, second, third inputs ( )-th and second, third inputs of the third majority elements are connected, respectively, to the outputs of the j -th majority element, the AND element and the outputs of the first, third exclusive OR elements, the first input of the second AND element and the output of the third majority element are connected, respectively, to the output of the second exclusive OR element and the second input of the second AND element, and the first inputs of the third, fourth majority elements and the first, second inputs of the first AND element are connected, respectively, to the third, second tuning and fourth, fifth information inputs of the logical module, the i -th information input of which is connected to the i -th input of the first majority element.

The drawing shows a diagram of the proposed logical module.

The logical module contains AND elements 1 ₁ , 1 ₂ , exclusive OR elements 2 ₁ , 2 ₂ , 2 ₃ and majority elements 3 ₁ , 3 ₂ , 3 ₃ , 3 ₄ , and the i -th ( ) input of element 3 _j ( ) and the first, second inputs of element 1 ₁ are connected, respectively, to the i -th input of element 2 _j and the first, second inputs of element 2 ₃ , the second, third inputs of element 3 _{2× j} and the second, third inputs of element 3 ₃ are connected, respectively, to the outputs of elements 3 _j , 1 _j and 2 ₁ , 2 ₃ , and the first, second inputs of element 1 ₂ and the first inputs of elements 3 ₂ , 3 ₄ , 3 ₃ , the first, second inputs of element 1 ₁ are connected respectively to the outputs of elements 2 ₂ , 3 ₃ and the first, second, third tuning, fourth, fifth information inputs of the logical module, the i -th information input and output of which are connected, respectively, to the i -th input of element 3 ₁ and the output of element 3 ₄ .

The operation of the proposed logical module is carried out as follows. Binary signals are supplied to its first,..., fifth information and first, second, third configuration inputs, respectively and signals constant settings. The table below shows the Z output values of the proposed logic module, obtained for all possible sets of signal values at 1) ; 2) , ; 3) , ; 4) , ; 5) , .

1) 2) 3) 4) 5) 1) 2) 3) 4) 5) Z Z Z Z Z Z Z Z Z Z 00 000 0 0 0 0 0 10 000 1 0 0 0 0 00 001 1 0 0 0 0 10 001 1 1 0 0 0 00 010 1 0 0 0 0 10 010 1 1 0 0 0 00 011 1 1 0 0 0 10 011 1 1 1 0 0 00 100 1 0 0 0 0 10 100 1 1 0 0 0 00 101 1 1 0 0 0 10 101 1 1 1 0 0 00 110 1 1 0 0 0 10 110 1 1 1 0 0 00 111 1 1 1 0 0 10 111 1 1 1 1 0 01 000 1 0 0 0 0 eleven 000 1 1 0 0 0 01 001 1 1 0 0 0 eleven 001 1 1 1 0 0 01 010 1 1 0 0 0 eleven 010 1 1 1 0 0 01 011 1 1 1 0 0 eleven 011 1 1 1 1 0 01 100 1 1 0 0 0 eleven 100 1 1 1 0 0 01 101 1 1 1 0 0 eleven 101 1 1 1 1 0 01 110 1 1 1 0 0 eleven 110 1 1 1 1 0 01 111 1 1 1 1 0 eleven 111 1 1 1 1 1

If the above m -th ( ) or the fifth set of signal values , then according to the presented table we have

or ,

Where there are simple symmetric Boolean functions of five arguments (see p. 126 in the book Pospelov D.A. Logical methods of analysis and synthesis of circuits. M.: Energia, 1974).

The above information allows us to conclude that the proposed logical module, using a constant setting, implements any of five simple symmetric Boolean functions, depending on five arguments - input binary signals. At the same time, the circuit of the proposed logical module is simpler than that of the prototype, since its price according to Quine is 24.

Information sources:

1. RF patent 2286594, cl. G06F7/57, 2006

2. RF patent 2621376, cl. G06F7/57, 2017

Claims (1)

A logical module designed to implement simple symmetric Boolean functions, containing two elements and and four majority elements, with the first input of the second and the output of the fourth majority elements connected, respectively, to the first tuning input and output of the logical module, characterized in that three exclusive elements are introduced into it OR, i -th ( ) input j -th ( ) of the majority element and the first, second inputs of the first AND element are connected, respectively, to the i -th input of the j -th and the first, second inputs of the third exclusive OR elements, second, third inputs ( )-th and second, third inputs of the third majority elements are connected, respectively, to the outputs of the j -x majority element, the AND element and the outputs of the first, third exclusive OR elements, the first input of the second AND element and the output of the third majority element are connected, respectively, to the output of the second exclusive OR element and the second input of the second AND element, and the first inputs of the third, fourth majority elements and the first, second inputs of the first AND element are connected, respectively, to the third, second tuning and fourth, fifth information inputs of the logical module, the i -th information input of which is connected to the i -th input of the first majority element.

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