RU2812683C1 - Majority module - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: majority module is designed to implement a majority function, the arguments of which are input binary signals, and can be used in digital computing systems as a means of preliminary information processing. The majority module contains fourteen AND elements (1₁, …, 1₁₄), eighteen EXCLUSIVE OR elements (2₁, …, 2₁₈), and NOT element (3). Due to these elements and the new scheme of their connection, implementation of the majority function of nine arguments is ensured.

EFFECT: functionality of the majority module has been expanded.

1 cl, 1 dwg, 2 tbl

Description

The invention relates to computer technology and can be used in the construction of automation equipment, functional units of control systems, etc.

Majority modules are known (see, for example, RF patent 2762545, class G06F7/57, 2021), which contain AND elements, exclusive OR elements and implement the majority function of seven arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using known majority modules is limited functionality due to the fact that the implementation of the majority function of nine arguments is not ensured.

The closest device of the same purpose to the claimed invention in terms of the set of features is the majority module adopted as a prototype (RF patent 2710877, class G06F7/57, 2020), which contains AND elements, exclusive OR elements and implements the majority function of seven arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using the prototype is limited functionality due to the fact that the implementation of the majority function of nine arguments is not ensured.

The technical result of the invention is to expand the functionality by ensuring the implementation of the majority function of nine arguments - input binary signals.

The specified technical result when implementing the invention is achieved by the fact that in the majority module containing ten AND elements and twelve exclusive OR elements, the first, second inputs of the i -th ( ) of the exclusive OR element are connected, respectively, to the first, second inputs of the i -th AND element, the peculiarity is that four elements and are additionally introduced into it, six exclusive OR elements and a NOT element, the first, second inputs of the j -th ( ) and the first, second inputs of the kth ( ) exclusive OR elements are connected respectively to the outputs ( )th, ( )-th and first, second inputs of k -th elements and, second inputs ( )th, ( )th, tenth elements AND and first, second inputs ( ) of the exclusive OR element are connected respectively to the outputs ( )-th, k -th, eighth elements exclusive OR and outputs ( )-th, k -th elements and, first, second inputs of the fourth, first, second inputs of the ninth and first, second inputs of the eleventh elements AND are connected, respectively, to the outputs of the thirteenth, fourteenth, outputs of the sixth, seventh and outputs of the fifth, fifteenth elements of the exclusive OR, the first inputs of the eighth, thirteenth, fourteenth AND elements, the input and output of the element are NOT connected, respectively, to the outputs of the twelfth, sixteenth, seventeenth, the first input of the eleventh exclusive OR elements and the first inputs of the tenth, twelfth AND elements, and the first input ( )th and first, second inputs ( )th elements AND are connected respectively with ( )-m and ( )-m, ( )-th inputs of the majority module, the output of which is connected to the output of the eighteenth exclusive OR element.

The drawing shows a diagram of the proposed majority module.

The majority module contains elements AND 1 ₁ ,…,1 ₁₄ , elements exclusive OR 2 ₁ ,…,2 ₁₈ and element NOT 3, with the first and second inputs of element 2 _i ( ) are connected respectively to the first, second inputs of element 1 _i , the first, second inputs of element 2 _k ( ) and the first, second inputs of element 2 _j ( ) are connected respectively to the first, second inputs of element 1 _k and outputs of elements 1 _{j -7} , 1 _{j -11} , the second inputs of elements 1 _{j -7} , 1 _{k +3} , 1 ₁₀ and the first, second inputs of element 2 _{k +7} are connected respectively with the outputs of elements 2 _{j -11} , 2 _k , 2 ₈ and 1 _{k +3} , 1 _k , the first, second inputs of element 1 ₄ , the first, second inputs of element 1 ₉ and the first, second inputs of element 1 ₁₁ are connected respectively to the outputs elements 2 ₁₃ , 2 ₁₄ , 2 ₆ , 2 ₇ and 2 ₅ , 2 ₁₅ , the first inputs of elements 1 ₈ , 1 ₁₃ , 1 ₁₄ , the input and output of element 3 are connected respectively to the outputs of elements 2 ₁₂ , 2 ₁₆ , 2 ₁₇ , the first input of element 2 ₁₁ and the first inputs of elements 1 ₁₀ , 1 ₁₂ , and the first input of element 1 _{k -4} and the first, second inputs of element 1 _{k -8} are connected respectively to ( )-m and ( )-m, ( )-th inputs of the majority module, the output of which is connected to the output of element 2 ₁₈ .

The operation of the proposed majority module is carried out as follows. Binary signals are supplied to its first,..., ninth inputs respectively . Table 1 and Table 2 below show the values of internal signals, respectively. ( ), of the proposed majority module, obtained for all possible sets of signal values , and the values of its output signal Z , obtained for all possible sets of signal values .

Table 1 000 00 100 01 001 01 101 10 010 01 110 10 011 10 111 eleven

table 2 Z Z 00 00 00 0 10 00 00 0 00 00 01 0 10 00 01 0 00 00 10 0 10 00 10 0 00 00 eleven 0 10 00 eleven 1 00 01 00 0 10 01 00 0 00 01 01 0 10 01 01 0 00 01 10 0 10 01 10 1 00 01 eleven 0 10 01 eleven 1 00 10 00 0 10 10 00 0 00 10 01 0 10 10 01 1 00 10 10 0 10 10 10 1 00 10 eleven 1 10 10 eleven 1 00 eleven 00 0 10 eleven 00 1 00 eleven 01 0 10 eleven 01 1 00 eleven 10 1 10 eleven 10 1 00 eleven eleven 1 10 eleven eleven 1 01 00 00 0 eleven 00 00 0 01 00 01 0 eleven 00 01 0 01 00 10 0 eleven 00 10 1 01 00 eleven 0 eleven 00 eleven 1 01 01 00 0 eleven 01 00 0 01 01 01 0 eleven 01 01 1 01 01 10 0 eleven 01 10 1 01 01 eleven 1 eleven 01 eleven 1 01 10 00 0 eleven 10 00 1 01 10 01 0 eleven 10 01 1 01 10 10 1 eleven 10 10 1 01 10 eleven 1 eleven 10 eleven 1 01 eleven 00 0 eleven eleven 00 1 01 eleven 01 1 eleven eleven 01 1 01 eleven 10 1 eleven eleven 10 1 01 eleven eleven 1 eleven eleven eleven 1

According to Table 1, Table 2, we have

,

Where there is a majority function of nine arguments .

The above information allows us to conclude that the proposed majority module has broader functionality compared to the prototype, since it implements the majority function of nine arguments - input binary signals.

Claims (1)

A majority module containing ten AND elements and twelve exclusive OR elements, with the first and second inputs of the i -th ( ) of the exclusive OR element are connected, respectively, to the first, second inputs of the i -th AND element, characterized in that four elements and are additionally introduced into it, six exclusive OR elements and a NOT element, the first, second inputs of the j -th ( ) and the first, second inputs of the kth ( ) exclusive OR elements are connected respectively to the outputs ( )th, ( )-th and first, second inputs of k -th elements and, second inputs ( )th, ( )th, tenth elements AND and first, second inputs ( ) of the exclusive OR element are connected respectively to the outputs ( )-th, k -th, eighth elements exclusive OR and outputs ( )-th, k -th elements and, first, second inputs of the fourth, first, second inputs of the ninth and first, second inputs of the eleventh elements AND are connected, respectively, to the outputs of the thirteenth, fourteenth, outputs of the sixth, seventh and outputs of the fifth, fifteenth elements of the exclusive OR, the first inputs of the eighth, thirteenth, fourteenth AND elements, the input and output of the element are NOT connected, respectively, to the outputs of the twelfth, sixteenth, seventeenth, the first input of the eleventh exclusive OR elements and the first inputs of the tenth, twelfth AND elements, and the first input ( )th and first, second inputs ( )th elements AND are connected respectively with ( )-m and ( )-m, ( )-th inputs of the majority module, the output of which is connected to the output of the eighteenth exclusive OR element.