RU2805141C1 - Majority module - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: majority module contains thirty-six 2OR elements and thirty-six 2AND elements.

EFFECT: reduced hardware costs and circuit depth while maintaining the functionality of the prototype.

1 cl, 1 dwg, 2 tbl

Description

The invention relates to computer technology and can be used in the construction of automation equipment, functional units of control systems, etc.

Majority modules are known (RF patent 2700552, class H03K19/23, 2019; RF patent 2764709, class G06F7/57, 2022), which contain 2I elements, 2OR elements and implement the majority function of seven arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using known majority modules is limited functionality due to the fact that the implementation of the majority function of thirteen arguments - input binary signals - is not ensured.

The closest device of the same purpose to the claimed invention in terms of the set of features is the majority module adopted as a prototype (RF patent 2628222, class G06F7/38, 2017), which contains 2I elements, 2OR elements and implements the majority function of thirteen arguments - input binary signals .

The reasons that prevent the achievement of the technical result indicated below when using the prototype include large circuit depth and hardware costs due to the fact that the circuit depth of the prototype is 13 and it contains 42 2ILI elements and 46 2I elements.

The technical result of the invention is to reduce hardware costs and circuit depth while maintaining the functionality of the prototype.

The specified technical result when implementing the invention is achieved by the fact that in the majority module containing thirty-six elements 2OR and thirty-six elements 2I, the peculiarity is that the first, second inputs of the i -th ( ) and the first, second inputs of the j -th ( ) elements 2I are connected respectively to the first, second inputs of the i -th and outputs of the j -th, ( )-th elements 2OR, first, second inputs of k -th ( ) and first, second inputs ( )-th elements 2I are connected respectively to the outputs ( )th, ( )-th elements 2I and outputs ( )th, ( )-th elements 2OR, first, second inputs ( )th and first, second inputs ( )-th elements 2I are connected respectively to the outputs of the k -th, ( )-th elements 2I and outputs ( )th, ( )th elements 2OR, first inputs ( )th, ( )th and outputs ( )th, ( )-th elements 2I are connected respectively to the outputs ( )-th, k -th elements of 2OR and second inputs ( )th, ( )th elements 2I, first inputs ( )th, ( )th, ( )th and outputs ( )th, ( )th, ( )th elements 2I are connected respectively to the outputs ( )th, ( )th, ( )th elements 2OR and second inputs ( )th, ( )th, ( )th elements 2I, first, second inputs of the thirtieth and first, second inputs ( )th elements 2I are connected respectively to the outputs of the thirty-fifth elements 2ILI, 2I and the outputs ( )th, ( )th elements 2I, first inputs of the twenty-fifth, ( )th, ( )th, ( )th, ( )th, thirty-fifth elements 2OR and first, second inputs ( )th, the second input of the thirty-sixth elements 2I are connected, respectively, to the second inputs of the thirty-fifth, ( )th, ( )th, ( )th, ( ) th, thirtieth element 2OR and outputs ( )th, ( )-th elements 2I, output of the thirty-sixth element 2OR, outputs ( )th, ( )th, ( )th elements 2I and ( )th, ( ) of the 2OR elements are connected respectively to the first inputs ( )th, ( )th, ( )th and ( )th, ( )-th elements of 2OR, the first input of the thirty-second element 2OR, the second input of the thirty-fifth element 2I and the first input of the thirty-fifth element 2I, the second input of the twenty-fifth element 2OR are connected, respectively, to the output of the seventeenth and the output of the eighteenth elements of 2OR, and the first inputs of the thirty-sixth elements 2AND, 2OR and first, second inputs ( )th, first, second inputs ( )th, first, second inputs ( )-th elements 2I are connected respectively to the outputs of the thirty-third, thirty-fourth elements 2I and ( )-mu, ( )-mu, ( )-mu, ( )-mu, ( )-mu, ( )-th inputs of the majority module, the thirteenth input and output of which are connected, respectively, to the second input of the thirty-sixth element 2OR and the output of the thirty-sixth element 2I.

The drawing shows a diagram of the proposed majority module.

The majority module contains elements 2I 1 ₁ ,…,1 ₃₆ and elements 2OR 2 ₁ ,…,2 ₃₆ , with the first and second inputs of element 1 _i ( ) and the first, second inputs of element 1 _j ( ) are connected respectively to the first, second inputs of element 2 _i and outputs of elements 2 _j , 2 _{j +5} , first, second inputs of element 1 _k ( ) and the first, second inputs of element 1 _{k +4} are connected respectively to the outputs of elements 1 _{k +6} , 1 _{k +8} and the outputs of elements 2 _{k +8} , 2 _{k +10} , the first, second inputs of element 1 _{k +12} and the first, the second inputs of element 1 _{k +16} are connected respectively to the outputs of elements 1 _k , 1 _{k +2} and the outputs of elements 2 _{k +2} , 2 _{k +4} , the first inputs of elements 1 _{k +2} , 1 _{k +14} and the outputs of elements 1 _{k + 10} , 1 _{k +4} are connected respectively to the outputs of elements 2 _{k +6} , 2 _k and the second inputs of elements 1 _{k +2} , 1 _{k +14} , the first inputs of elements 1 _{k +18} , 1 _{k +20} , 1 _{k +22} and the outputs of elements 1 _{k +14} , 1 _{k +16} , 1 _{k +20} are connected, respectively, to the outputs of elements 2 _{k +12} , 2 _{k +14} , 2 _{k +18} and the second inputs of elements 1 _{k +18} , 1 _{k +20} , 1 _{k +22} , first, second inputs of element 1 ₃₀ and first, second inputs of element 1 _{k +30} are connected respectively to the outputs of elements 2 ₃₅ , 1 ₃₅ and outputs of elements 1 _{3× k +22} , 1 _{3× k +23} , first inputs elements 2 ₂₅ , 2 _{k +25} , 2 _{k +27} , 2 _{k +29} , 2 _{k +32} , 2 ₃₅ and the first, second inputs of element 1 _{k +32} , second input of element 1 ₃₆ are connected respectively to the second inputs of elements 2 ₃₅ , 2 _{30– k} , 2 _{33– k} , 2 _{35– k} , 2 _{28– k} , 2 ₃₀ and element outputs 1 _{k +30} , 1 _{3× k +24} , 2 ₃₆ , element outputs 1 _{k +12} , 1 _{k +18} , 1 _{k +22} , 2 _{k +20} , 2 _{k +22} are connected respectively to the first inputs of elements 2 _{3× k +22} , 2 _{3× k +27} , 2 _{3× k +23} , 2 _{8× k +19} , 2 _{3× k +28} , the first input of element 2 ₃₂ , the second input of element 1 ₃₅ and the first input of element 1 ₃₅ , the second input of element 2 ₂₅ connected respectively to the output of element 2 ₁₇ and the output of element 2 ₁₈ , and the first inputs of elements 1 ₃₆ , 2 ₃₆ and the first, second inputs of element 1 _{k +6} , first, second inputs of element 1 _{k +8} , first, second inputs of element 1 _{k +10} are connected respectively to the outputs of elements 1 ₃₃ , 1 ₃₄ and ( )-mu, ( )-mu, ( )-mu, ( )-mu, ( )-mu, ( )-th inputs of the majority module, the thirteenth input and output of which are connected, respectively, to the second input of element 2 ₃₆ and the output of element 1 ₃₆ .

The operation of the proposed majority module is carried out as follows. Binary signals are supplied to its first,..., thirteenth inputs, respectively . Table 1 and Table 2 below show the values of internal signals, respectively. ( ) of the proposed majority module, obtained for all possible sets of signal values , and the values of its output signal Z , obtained for all possible sets of signal values .

Table 1

x _{6× k – 5}
x _{6× k – 4}
x _{6× k –3}
x _{6× k –2}
x _{6× k -1}
x _{6× k} y _{6× k}
y _{6× k – 1}
y _{6× k –2}
y _{6× k –3}
y _{6× k -4}
y _{6× k -5} x _{6× k – 5}
x _{6× k – 4}
x _{6× k –3}
x _{6× k –2}
x _{6× k -1}
x _{6× k} y _{6× k}
y _{6× k – 1}
y _{6× k –2}
y _{6× k –3}
y _{6× k -4}
y _{6× k -5} 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 1 1 1 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 1 1 0 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

table 2

0 000000 000000 0 1 000000 000000 0 0 000000 000001 0 1 000000 000001 0 0 000000 000011 0 1 000000 000011 0 0 000000 000111 0 1 000000 000111 0 0 000000 001111 0 1 000000 001111 0 0 000000 011111 0 1 000000 011111 0 0 000000 111111 0 1 000000 111111 1 0 000001 000000 0 1 000001 000000 0 0 000001 000001 0 1 000001 000001 0 0 000001 000011 0 1 000001 000011 0 0 000001 000111 0 1 000001 000111 0 0 000001 001111 0 1 000001 001111 0 0 000001 011111 0 1 000001 011111 1 0 000001 111111 1 1 000001 111111 1 0 000011 000000 0 1 000011 000000 0 0 000011 000001 0 1 000011 000001 0 0 000011 000011 0 1 000011 000011 0 0 000011 000111 0 1 000011 000111 0 0 000011 001111 0 1 000011 001111 1 0 000011 011111 1 1 000011 011111 1 0 000011 111111 1 1 000011 111111 1 0 000111 000000 0 1 000111 000000 0 0 000111 000001 0 1 000111 000001 0 0 000111 000011 0 1 000111 000011 0 0 000111 000111 0 1 000111 000111 1 0 000111 001111 1 1 000111 001111 1 0 000111 011111 1 1 000111 011111 1 0 000111 111111 1 1 000111 111111 1 0 001111 000000 0 1 001111 000000 0 0 001111 000001 0 1 001111 000001 0 0 001111 000011 0 1 001111 000011 1 0 001111 000111 1 1 001111 000111 1 0 001111 001111 1 1 001111 001111 1 0 001111 011111 1 1 001111 011111 1 0 001111 111111 1 1 001111 111111 1 0 011111 000000 0 1 011111 000000 0 0 011111 000001 0 1 011111 000001 1 0 011111 000011 1 1 011111 000011 1 0 011111 000111 1 1 011111 000111 1 0 011111 001111 1 1 011111 001111 1 0 011111 011111 1 1 011111 011111 1 0 011111 111111 1 1 011111 111111 1 0 111111 000000 0 1 111111 000000 1 0 111111 000001 1 1 111111 000001 1 0 111111 000011 1 1 111111 000011 1 0 111111 000111 1 1 111111 000111 1 0 111111 001111 1 1 111111 001111 1 0 111111 011111 1 1 111111 011111 1 0 111111 111111 1 1 111111 111111 1

According to Table 1, Table 2 we have

,

Where there is a majority function of thirteen arguments . In this case, the circuit depth of the proposed majority module is 11.

The above information allows us to conclude that the proposed majority module implements the majority function of thirteen arguments - input binary signals and has less circuit depth and hardware costs compared to the prototype.

Claims (1)

A majority module containing thirty-six 2OR elements and thirty-six 2I elements, characterized in that the first and second inputs of the i -th ( ) and the first, second inputs of the j -th ( ) elements 2I are connected respectively to the first, second inputs of the i -th and outputs of the j -th, ( )-th elements 2OR, first, second inputs of k -th ( ) and first, second inputs ( )-th elements 2I are connected respectively to the outputs ( )th, ( )-th elements 2I and outputs ( )th, ( )-th elements 2OR, first, second inputs ( )th and first, second inputs ( )-th elements 2I are connected respectively to the outputs of the k -th, ( )-th elements 2I and outputs ( )th, ( )th elements 2OR, first inputs ( )th, ( )th and outputs ( )th, ( )-th elements 2I are connected respectively to the outputs ( )-th, k -th elements of 2OR and second inputs ( )th, ( )th elements 2I, first inputs ( )th, ( )th, ( )th and outputs ( )th, ( )th, ( )th elements 2I are connected respectively to the outputs ( )th, ( )th, ( )th elements 2OR and second inputs ( )th, ( )th, ( )th elements 2I, first, second inputs of the thirtieth and first, second inputs ( )th elements 2I are connected respectively to the outputs of the thirty-fifth elements 2ILI, 2I and the outputs ( )th, ( )th elements 2I, first inputs of the twenty-fifth, ( )th, ( )th, ( )th, ( )th, thirty-fifth elements 2OR and first, second inputs ( )th, the second input of the thirty-sixth elements 2I are connected, respectively, to the second inputs of the thirty-fifth, ( )th, ( )th, ( )th, ( ) th, thirtieth element 2OR and outputs ( )th, ( )-th elements 2I, output of the thirty-sixth element 2OR, outputs ( )th, ( )th, ( )th elements 2I and ( )th, ( ) of the 2OR elements are connected respectively to the first inputs ( )th, ( )th, ( )th and ( )th, ( )-th elements of 2OR, the first input of the thirty-second element 2OR, the second input of the thirty-fifth element 2I and the first input of the thirty-fifth element 2I, the second input of the twenty-fifth element 2OR are connected, respectively, to the output of the seventeenth and the output of the eighteenth elements of 2OR, and the first inputs of the thirty-sixth elements 2AND, 2OR and first, second inputs ( )th, first, second inputs ( )th, first, second inputs ( )-th elements 2I are connected respectively to the outputs of the thirty-third, thirty-fourth elements 2I and ( )-mu, ( )-mu, ( )-mu, ( )-mu, ( )-mu, ( )-th inputs of the majority module, the thirteenth input and output of which are connected, respectively, to the second input of the thirty-sixth element 2OR and the output of the thirty-sixth element 2I.