RU2803610C1 - Majority module - Google Patents

Abstract

FIELD: majority modules.

SUBSTANCE: majority module contains twenty-one majority elements (1₁,…,1₂₁).

EFFECT: reduction in the relative indicator of the circuit depth while maintaining the elemental basis of the prototype.

1 cl, 1 dwg, 4 tbl

Description

The invention relates to computer technology and can be used to build automation equipment, functional units of control systems, etc.

Majority modules are known (see, for example, RF patent 2580801, class H03K 19/23, 2016), which contain logical elements and implement the majority function of five arguments - input binary signals or a disjunction (conjunction) of the same five arguments. Wherein $$\tilde{h}=\frac{h}{n}=\frac{4}{5}$$ , where n , h and $$\tilde{h}$$ there is, respectively, the number of arguments of the implemented functions, the circuit depth, in particular, of the mentioned analogue and its relative indicator.

The reasons that prevent the achievement of the technical result indicated below when using known majority modules include the large value of the relative indicator of circuit depth, the presence in the hardware, in particular, of the mentioned analogue of AND, OR elements and limited functionality due to the fact that the implementation of majority control is not ensured. functions of nine arguments - input binary signals or disjunction (conjunction) of the same nine arguments.

The closest device of the same purpose to the claimed invention in terms of the set of features is the majority module adopted as a prototype (RF patent 2700553, class H03K 19/23, 2019), which contains majority elements and implements the majority function of five arguments - input binary signals or disjunction (conjunction) of the same five arguments. In this case, the relative indicator of the circuit depth of the prototype is $$\tilde{h}=\frac{4}{5}$$ .

The reasons that prevent the achievement of the technical result indicated below when using the prototype include the large value of the relative indicator of circuit depth and limited functionality due to the fact that the implementation of the majority function of nine arguments - input binary signals or disjunction (conjunction) of the same nine arguments - is not ensured.

The technical result of the invention is to expand the functionality by ensuring the implementation of the majority function of nine arguments - input binary signals or disjunction (conjunction) of the same nine arguments and reducing the relative indicator of circuit depth while maintaining the elemental basis of the prototype.

The specified technical result in the implementation of the invention is achieved by the fact that in the majority module containing nine majority elements, which have three inputs each, the mth outputs ( $$m=\overline{1.2}$$ ), ( $$m+4$$ )-th and first input of the m -th majority elements are connected respectively to the second inputs ( $$m+1$$ )th, ( $$m+5$$ )-th majority elements and the first tuning input of the majority module, the peculiarity is that twelve similar majority elements, the outputs of the third, seventh, i -th ( $$i=\overline{9.12}$$ ) and the first, second, third inputs of the twentieth majority elements are connected, respectively, to the second inputs of the fourth, eighth, ( $$i+4$$ )-th and outputs of the seventeenth, eighteenth, nineteenth majority elements, outputs ( $$m+12$$ )th, ( $$m+14$$ )th and first, second, third inputs of the twenty-first majority elements are connected respectively to the third inputs ( $$m+2$$ )th, ( $$m+6$$ )th and the outputs of the fourth, twentieth, eighth majority elements, and the first inputs ( $$m+6$$ )th, ( $$m+8$$ )th, ( $$m+12$$ )-th and the output of the twenty-first majority elements are connected, respectively, to the first tuning input and output of the majority module, the second tuning input of which is connected to the first inputs ( $$m+2$$ )th, ( $$m+4$$ )th, ( $$m+10$$ )th, ( $$m+14$$ )-th majority elements.

The drawing shows a diagram of the proposed majority module.

The majority module contains majority elements 1 ₁ ,…,1 ₂₁ , and the outputs of elements 1 _j ( $$j=\overline{1.3}$$ ), 1 _{j +4} , 1 _i ( $$i=\overline{9.12}$$ ) and third inputs of elements 1 _k ( $$k=\overline{3.4}$$ ), 1 _{k +4} are connected respectively to the second inputs of elements 1 _{j +1} , 1 _{j +5} , 1 _{i +4} and outputs of elements 1 _{k +10} , 1 _{k +12} , the first, second, third inputs of element 1 ₂₀ and outputs elements 1 ₄ , 1 ₂₀ , 1 ₈ are connected respectively to the outputs of elements 1 ₁₇ , 1 ₁₈ , 1 ₁₉ and the first, second, third inputs of element 1 ₂₁ , and the first inputs of elements 1 _{k –2} , 1 _{k +4} , 1 _{k + 6} , 1 _{k +10} and the output of element 1 ₂₁ are connected, respectively, to the first tuning input and output of the majority module, the second tuning input of which is connected to the first inputs of elements 1 _k , 1 _{k +2} , 1 _{k +8} , 1 _{k +12} .

The operation of the proposed majority module is carried out as follows. At its first and second tuning inputs, the necessary signals are fixed accordingly $$y_1,y_2\in \left\{0.1\right\}$$ constant settings. To the second inputs of elements 1 ₁ , 1 ₅ , the first input of element 1 ₁₇ ; third inputs of elements 1 ₁ , 1 ₅ , second input of element 1 ₁₇ ; third inputs of elements 1 ₂ , 1 ₆ , 1 ₁₇ ; second inputs of elements 1 ₉ , 1 ₁₁ , first input of element 1 ₁₈ ; third inputs of elements 1 ₉ , 1 ₁₁ , second input of element 1 ₁₈ ; third inputs of elements 1 ₁₃ , 1 ₁₅ , 1 ₁₈ ; second inputs of elements 1 ₁₀ , 1 ₁₂ , first input of element 1 ₁₉ ; the third inputs of elements 1 ₁₀ , 1 ₁₂ , the second input of element 1 ₁₉ and the third inputs of elements 1 ₁₄ , 1 ₁₆ , 1 ₁₉ are supplied respectively binary signals $$x_1$$ ; $$x_2$$ ; $$x_3$$ ; $$x_4$$ ; $$x_5$$ ; $$x_6$$ ; $$x_7$$ ; $$x_8$$ And $$x_9$$ ( $$x_1\mathrm{,...,}{x}_9\in \left\{0.1\right\}$$ ). Table 1 below shows the values of internal signals $$z_{3\times j-2}$$ ( $$j=\overline{1.3}$$ ), $$z_{3\times j-1}$$ , $$z_{3\times j}$$ of the proposed majority module, obtained for all possible sets of signal values $$x_{3\times j-2},x_{3\times j-1},x_{3\times j}$$ at $$y_1=1$$ , $$y_2=0$$ ; $$y_1=y_2=1$$ ; $$y_1=y_2=0$$ . Further in Table 2, Table 3, Table 4 the values of its output signal Z are given, obtained for all possible sets of signal values $$z_1\mathrm{,...,}{z}_9$$ at $$y_1=1$$ , $$y_2=0$$ ; $$y_1=y_2=1$$ ; $$y_1=y_2=0$$ .

Table 1

$$x_{3\times j-2}{x}_{3\times j-1}{x}_{3\times j}$$ $$y_1=1$$ , $$y_2=0$$ $$y_1=y_2=1$$ $$y_1=y_2=0$$ $$z_{3\times j}{z}_{3\times j-1}{z}_{3\times j-2}$$ $$z_{3\times j}{z}_{3\times j-1}{z}_{3\times j-2}$$ $$z_{3\times j}{z}_{3\times j-1}{z}_{3\times j-2}$$ 000 000 000 000 001 001 101 000 010 001 101 000 011 011 111 010 100 001 101 000 101 011 111 010 110 011 111 010 111 111 111 111

table 2

$$y_1=1$$ , $$y_2=0$$ $$y_1=1$$ , $$y_2=0$$ $$z_9{z}_8{z}_7$$ $$z_6{z}_5{z}_4$$ $$z_3{z}_2{z}_1$$ Z $$z_9{z}_8{z}_7$$ $$z_6{z}_5{z}_4$$ $$z_3{z}_2{z}_1$$ Z 000 000 000 0 011 000 000 0 000 000 001 0 011 000 001 0 000 000 011 0 011 000 011 0 000 000 111 0 011 000 111 1 000 001 000 0 011 001 000 0 000 001 001 0 011 001 001 0 000 001 011 0 011 001 011 1 000 001 111 0 011 001 111 1 000 011 000 0 011 011 000 0 000 011 001 0 011 011 001 1 000 011 011 0 011 011 011 1 000 011 111 1 011 011 111 1 000 111 000 0 011 111 000 1 000 111 001 0 011 111 001 1 000 111 011 1 011 111 011 1 000 111 111 1 011 111 111 1 001 000 000 0 111 000 000 0 001 000 001 0 111 000 001 0 001 000 011 0 111 000 011 1 001 000 111 0 111 000 111 1 001 001 000 0 111 001 000 0 001 001 001 0 111 001 001 1 001 001 011 0 111 001 011 1 001 001 111 1 111 001 111 1 001 011 000 0 111 011 000 1 001 011 001 0 111 011 001 1 001 011 011 1 111 011 011 1 001 011 111 1 111 011 111 1 001 111 000 0 111 111 000 1 001 111 001 1 111 111 001 1 001 111 011 1 111 111 011 1 001 111 111 1 111 111 111 1

Table 3

$$y_1=y_2=1$$ $$y_1=y_2=1$$ $$z_9{z}_8{z}_7$$ $$z_6{z}_5{z}_4$$ $$z_3{z}_2{z}_1$$ Z $$z_9{z}_8{z}_7$$ $$z_6{z}_5{z}_4$$ $$z_3{z}_2{z}_1$$ Z 000 000 000 0 101 111 000 1 000 000 101 1 101 111 101 1 000 000 111 1 101 111 111 1 000 101 000 1 111 000 000 1 000 101 101 1 111 000 101 1 000 101 111 1 111 000 111 1 000 111 000 1 111 101 000 1 000 111 101 1 111 101 101 1 000 111 111 1 111 101 111 1 101 000 000 1 111 111 000 1 101 000 101 1 111 111 101 1 101 000 111 1 111 111 111 1 101 101 000 1 101 101 101 1 101 101 111 1

Table 4

$$y_1=y_2=0$$ $$y_1=y_2=0$$ $$z_9{z}_8{z}_7$$ $$z_6{z}_5{z}_4$$ $$z_3{z}_2{z}_1$$ Z $$z_9{z}_8{z}_7$$ $$z_6{z}_5{z}_4$$ $$z_3{z}_2{z}_1$$ Z 000 000 000 0 010 111 000 0 000 000 010 0 010 111 010 0 000 000 111 0 010 111 111 0 000 010 000 0 111 000 000 0 000 010 010 0 111 000 010 0 000 010 111 0 111 000 111 0 000 111 000 0 111 010 000 0 000 111 010 0 111 010 010 0 000 111 111 0 111 010 111 0 010 000 000 0 111 111 000 0 010 000 010 0 111 111 010 0 010 000 111 0 111 111 111 1 010 010 000 0 010 010 010 0 010 010 111 0

If $$y_1=1$$ , $$y_2=0$$ or $$y_1=y_2=1$$ or $$y_1=y_2=0$$ , then according to the presented tables we have

$$Z=\{\begin{array}{l}1\text{at}{\displaystyle \sum _{q=1}^9{x}_q}\ge 5\hfill \\ 0\text{at}{\displaystyle \sum _{q=1}^9{x}_q}<5\hfill \end{array}=\text{Maj}(x_1\mathrm{,...,}{x}_9)$$ or $$Z=\{\begin{array}{l}1\text{at}{\displaystyle \sum _{q=1}^9{x}_q}>0\hfill \\ 0\text{at}{\displaystyle \sum _{q=1}^9{x}_q}=0\hfill \end{array}=x_1\vee \mathrm{...}\vee x_9$$ or $$Z=\{\begin{array}{l}1\text{at}{\displaystyle \sum _{q=1}^9{x}_q}=9\hfill \\ 0\text{at}{\displaystyle \sum _{q=1}^9{x}_q}<9\hfill \end{array}=x_1\wedge \mathrm{...}\wedge x_9$$ ,

Where $$\text{Maj}(x_1\mathrm{,...,}{x}_9)$$ And $$x_1\vee \mathrm{...}\vee x_9$$ , $$x_1\wedge \mathrm{...}\wedge x_9$$ there is a majoritarian function and a disjunction, a conjunction of nine arguments $$x_1\mathrm{,...,}{x}_9$$ .

The above information allows us to conclude that the proposed majority module is built in the elemental basis of the prototype and has broader functionality compared to the prototype, since it implements the majority function of nine arguments - input binary signals or a disjunction (conjunction) of the same nine arguments. In this case, the relative indicator of the circuit depth of the proposed majority module is $$\tilde{h}=\frac{5}{9}<\frac{4}{5}$$ .

Claims (1)

A majority module containing nine majority elements, which have three inputs each, with the mth outputs ( $$m=\overline{1.2}$$ ), ( $$m+4$$ )-th and first input of the m -th majority elements are connected respectively to the second inputs ( $$m+1$$ )th, ( $$m+5$$ )-th majority elements and the first tuning input of the majority module, characterized in that twelve similar majority elements, the outputs of the third, seventh, i -th ( $$i=\overline{9.12}$$ ) and the first, second, third inputs of the twentieth majority elements are connected, respectively, to the second inputs of the fourth, eighth, ( $$i+4$$ )-th and outputs of the seventeenth, eighteenth, nineteenth majority elements, outputs ( $$m+12$$ )th, ( $$m+14$$ )th and first, second, third inputs of the twenty-first majority elements are connected respectively to the third inputs ( $$m+2$$ )th, ( $$m+6$$ )th and the outputs of the fourth, twentieth, eighth majority elements, and the first inputs ( $$m+6$$ )th, ( $$m+8$$ )th, ( $$m+12$$ )-th and the output of the twenty-first majority elements are connected, respectively, to the first tuning input and output of the majority module, the second tuning input of which is connected to the first inputs ( $$m+2$$ )th, ( $$m+4$$ )th, ( $$m+10$$ )th, ( $$m+14$$ )-th majority elements.