RU2191444C1 - Способ изготовления полевого транзистора с периодически легированным каналом - Google Patents

Способ изготовления полевого транзистора с периодически легированным каналом Download PDF

Info

Publication number
RU2191444C1
RU2191444C1 RU2001127264/28A RU2001127264A RU2191444C1 RU 2191444 C1 RU2191444 C1 RU 2191444C1 RU 2001127264/28 A RU2001127264/28 A RU 2001127264/28A RU 2001127264 A RU2001127264 A RU 2001127264A RU 2191444 C1 RU2191444 C1 RU 2191444C1
Authority
RU
Russia
Prior art keywords
silicon
nanostructure
channel
transistor
layer
Prior art date
Application number
RU2001127264/28A
Other languages
English (en)
Russian (ru)
Inventor
В.К. Смирнов
Д.С. Кибалов
В.А. Гергель
Original Assignee
Общество с ограниченной ответственностью "Агентство маркетинга научных разработок"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Общество с ограниченной ответственностью "Агентство маркетинга научных разработок" filed Critical Общество с ограниченной ответственностью "Агентство маркетинга научных разработок"
Priority to RU2001127264/28A priority Critical patent/RU2191444C1/ru
Priority to PCT/GB2002/001948 priority patent/WO2003032398A2/fr
Priority to EP02720273A priority patent/EP1464086A2/fr
Application granted granted Critical
Publication of RU2191444C1 publication Critical patent/RU2191444C1/ru

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
RU2001127264/28A 2001-10-09 2001-10-09 Способ изготовления полевого транзистора с периодически легированным каналом RU2191444C1 (ru)

Priority Applications (3)

Application Number Priority Date Filing Date Title
RU2001127264/28A RU2191444C1 (ru) 2001-10-09 2001-10-09 Способ изготовления полевого транзистора с периодически легированным каналом
PCT/GB2002/001948 WO2003032398A2 (fr) 2001-10-09 2002-04-26 Transistor a effet de champ avec canal periodiquement dope
EP02720273A EP1464086A2 (fr) 2001-10-09 2002-04-26 Transistor a effet de champ avec canal periodiquement dope

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
RU2001127264/28A RU2191444C1 (ru) 2001-10-09 2001-10-09 Способ изготовления полевого транзистора с периодически легированным каналом

Publications (1)

Publication Number Publication Date
RU2191444C1 true RU2191444C1 (ru) 2002-10-20

Family

ID=20253616

Family Applications (1)

Application Number Title Priority Date Filing Date
RU2001127264/28A RU2191444C1 (ru) 2001-10-09 2001-10-09 Способ изготовления полевого транзистора с периодически легированным каналом

Country Status (3)

Country Link
EP (1) EP1464086A2 (fr)
RU (1) RU2191444C1 (fr)
WO (1) WO2003032398A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2754995C1 (ru) * 2020-11-23 2021-09-08 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Способ изготовления тонкопленочного транзистора

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1672415A1 (fr) * 2004-12-17 2006-06-21 Freewire Limited Méthode pour former une structure nano-relief sur la surface d'un film
WO2013022365A1 (fr) 2011-08-05 2013-02-14 Wostec, Inc. Diode électroluminescente comportant une couche nanostructurée et ses procédés de fabrication et d'utilisation
US9653627B2 (en) 2012-01-18 2017-05-16 Wostec, Inc. Arrangements with pyramidal features having at least one nanostructured surface and methods of making and using
US9500789B2 (en) 2013-03-13 2016-11-22 Wostec, Inc. Polarizer based on a nanowire grid
WO2015199573A1 (fr) 2014-06-26 2015-12-30 Wostec, Inc. Nanomasque dur de type onde aligné sur une caractéristique topographique ainsi que procédé de fabrication et d'utilisation
US10672427B2 (en) 2016-11-18 2020-06-02 Wostec, Inc. Optical memory devices using a silicon wire grid polarizer and methods of making and using
WO2018156042A1 (fr) 2017-02-27 2018-08-30 Wostec, Inc. Polariseur à grille de nanofils sur une surface incurvée et procédés de fabrication et d'utilisation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5050878A (fr) * 1973-09-05 1975-05-07
JPS61185973A (ja) * 1985-02-13 1986-08-19 Nec Corp 半導体装置
RU2173003C2 (ru) * 1999-11-25 2001-08-27 Септре Электроникс Лимитед Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Гергель В.А., Мокеров В.Г. Доклады Академии Наук, 2000, т. 375, № 5, с. 609-610. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2754995C1 (ru) * 2020-11-23 2021-09-08 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Способ изготовления тонкопленочного транзистора

Also Published As

Publication number Publication date
WO2003032398A3 (fr) 2003-07-03
WO2003032398A2 (fr) 2003-04-17
EP1464086A2 (fr) 2004-10-06

Similar Documents

Publication Publication Date Title
US6107130A (en) CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
US5766969A (en) Multiple spacer formation/removal technique for forming a graded junction
US7071065B1 (en) Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US6187620B1 (en) Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
US7094639B2 (en) Method for fabricating semiconductor device
US5656518A (en) Method for fabrication of a non-symmetrical transistor
JP2551940B2 (ja) 半導体素子の製造方法
KR20020097202A (ko) 반도체장치의 제조방법
TW560069B (en) Groove gate field-effect transistor and method of manufacturing the same
US5654215A (en) Method for fabrication of a non-symmetrical transistor
JP5379489B2 (ja) 歪みシリコンにおける欠陥低減のための窒素ベース注入物
RU2191444C1 (ru) Способ изготовления полевого транзистора с периодически легированным каналом
US6355963B1 (en) MOS type semiconductor device having an impurity diffusion layer
EP1594166A2 (fr) Dispositif semiconducteur et méthode pour sa fabrication
KR100713267B1 (ko) 반도체 디바이스 제조 방법
JP2005051140A (ja) 半導体装置およびその製造方法
TW200308001A (en) Semiconductor device having gate with negative slope and method for manufacturing the same
US5851888A (en) Controlled oxide growth and highly selective etchback technique for forming ultra-thin oxide
JPH08264789A (ja) 絶縁ゲート半導体装置および製造方法
JPS626671B2 (fr)
JPS63281465A (ja) 電界効果トランジスタ及びその中間体の製造方法
JP2003517204A (ja) 炭化ケイ素半導体装置においてより高い反転層移動度を得る方法
US20050048707A1 (en) Processing method for improving structure of a high voltage device
JPS6318346B2 (fr)
KR101131418B1 (ko) 반도체 소자 및 이의 제조 방법

Legal Events

Date Code Title Description
MM4A The patent is invalid due to non-payment of fees

Effective date: 20041009

NF4A Reinstatement of patent
PC4A Invention patent assignment

Effective date: 20060328

NF4A Reinstatement of patent

Effective date: 20110627