WO2003032398A3 - Transistor a effet de champ avec canal periodiquement dope - Google Patents

Transistor a effet de champ avec canal periodiquement dope Download PDF

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Publication number
WO2003032398A3
WO2003032398A3 PCT/GB2002/001948 GB0201948W WO03032398A3 WO 2003032398 A3 WO2003032398 A3 WO 2003032398A3 GB 0201948 W GB0201948 W GB 0201948W WO 03032398 A3 WO03032398 A3 WO 03032398A3
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
channel
nanostructure
wavelength
conductivity type
Prior art date
Application number
PCT/GB2002/001948
Other languages
English (en)
Other versions
WO2003032398A2 (fr
Inventor
Valery Smirnov
Dimitry Kibalov
Victor Gergel
Original Assignee
Sceptre Electronics Ltd
Valery Smirnov
Dimitry Kibalov
Victor Gergel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sceptre Electronics Ltd, Valery Smirnov, Dimitry Kibalov, Victor Gergel filed Critical Sceptre Electronics Ltd
Priority to EP02720273A priority Critical patent/EP1464086A2/fr
Publication of WO2003032398A2 publication Critical patent/WO2003032398A2/fr
Publication of WO2003032398A3 publication Critical patent/WO2003032398A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Cette invention se rapporte à un procédé qui sert à fabriquer un transistor à effet de champ avec canal périodiquement dopé et qui consiste à cet effet à sélectionner une longueur d'onde d'une nanostructure à ordre d'ondes G2/α2 fois inférieure à la longueur du canal du transistor, G représentant le gain souhaité dans la transconductance du transistor et dans la fréquence de travail due au dopage périodique du canal, et α représentant le rapport entre la longueur d'onde et la distance séparant les régions dopées ; à former une mince couche d'oxyde de silicium de criblage sur la surface d'une région de transistor d'un premier type de conductivité, à déposer une couche de silicium amorphe ; à pulvériser sur la surface du silicium amorphe un flux d'ions moléculaires d'azote sous vide, afin de former la nanostructure, à diriger le plan d'incidence des ions le long du canal de transistor, à déterminer l'énergie ionique et l'angle d'incidence des ions sur la surface de silicium amorphe sur la base de la longueur d'onde de la nanostructure ; à transformer la nanostructure en nanomasque par plasma ionique réactif ; à implanter les ions dopants, afin de former dans la région de canal du transistor des implants peu profonds du second type de conductivité identique à celui des régions de source et de drain du transistor et opposé au premier type de conductivité ; à éliminer le nanomasque et l'oxyde de silicium de criblage ; et à former un matériau diélectrique de grille, une grille et des régions de source et de drain pour terminer la fabrication du transistor.
PCT/GB2002/001948 2001-10-09 2002-04-26 Transistor a effet de champ avec canal periodiquement dope WO2003032398A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP02720273A EP1464086A2 (fr) 2001-10-09 2002-04-26 Transistor a effet de champ avec canal periodiquement dope

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2001127264/28A RU2191444C1 (ru) 2001-10-09 2001-10-09 Способ изготовления полевого транзистора с периодически легированным каналом
RU2001127264 2001-10-09

Publications (2)

Publication Number Publication Date
WO2003032398A2 WO2003032398A2 (fr) 2003-04-17
WO2003032398A3 true WO2003032398A3 (fr) 2003-07-03

Family

ID=20253616

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/001948 WO2003032398A2 (fr) 2001-10-09 2002-04-26 Transistor a effet de champ avec canal periodiquement dope

Country Status (3)

Country Link
EP (1) EP1464086A2 (fr)
RU (1) RU2191444C1 (fr)
WO (1) WO2003032398A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1672415A1 (fr) * 2004-12-17 2006-06-21 Freewire Limited Méthode pour former une structure nano-relief sur la surface d'un film
RU2569638C2 (ru) 2011-08-05 2015-11-27 Востек, Инк. Светоизлучающий диод с наноструктурированным слоем и способы изготовления и применения
WO2013109157A1 (fr) 2012-01-18 2013-07-25 Wostec, Inc. Agencements à caractéristiques pyramidales ayant au moins une surface nanostructurée et leurs procédés de fabrication et d'utilisation
US9500789B2 (en) 2013-03-13 2016-11-22 Wostec, Inc. Polarizer based on a nanowire grid
US20170194167A1 (en) 2014-06-26 2017-07-06 Wostec, Inc. Wavelike hard nanomask on a topographic feature and methods of making and using
WO2018093284A1 (fr) 2016-11-18 2018-05-24 Wostec, Inc. Dispositifs de mémoire optique utilisant un polariseur à grille en fil de silicium et procédés de fabrication et d'utilisation
WO2018156042A1 (fr) 2017-02-27 2018-08-30 Wostec, Inc. Polariseur à grille de nanofils sur une surface incurvée et procédés de fabrication et d'utilisation
RU2754995C1 (ru) * 2020-11-23 2021-09-08 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Способ изготовления тонкопленочного транзистора

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5050878A (fr) * 1973-09-05 1975-05-07
US4831422A (en) * 1985-02-13 1989-05-16 Nec Corporation Field effect transistor
EP1104011A1 (fr) * 1999-11-25 2001-05-30 Sceptre Electronics Limited Procédé de formation de nanostructures en silicium, matrice de fils quantiques et composants basés sur ladite matrice

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5050878A (fr) * 1973-09-05 1975-05-07
US4831422A (en) * 1985-02-13 1989-05-16 Nec Corporation Field effect transistor
EP1104011A1 (fr) * 1999-11-25 2001-05-30 Sceptre Electronics Limited Procédé de formation de nanostructures en silicium, matrice de fils quantiques et composants basés sur ladite matrice

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GERGEL V A ET AL: "ENHANCEMENT OF OPERATION SPEED IN FIELD-EFFECT TRANSISTORS USING CHANNEL PROFILING", DOKLADY AKADEMII NAUK. ROSSIJSKA AKADEMI NAUK, NAUKA, MOSCOW, RU, vol. 375, no. 5, December 2000 (2000-12-01), pages 609 - 610, XP001149896, ISSN: 0869-5652 *

Also Published As

Publication number Publication date
RU2191444C1 (ru) 2002-10-20
WO2003032398A2 (fr) 2003-04-17
EP1464086A2 (fr) 2004-10-06

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