WO2003032398A2 - Transistor a effet de champ avec canal periodiquement dope - Google Patents
Transistor a effet de champ avec canal periodiquement dope Download PDFInfo
- Publication number
- WO2003032398A2 WO2003032398A2 PCT/GB2002/001948 GB0201948W WO03032398A2 WO 2003032398 A2 WO2003032398 A2 WO 2003032398A2 GB 0201948 W GB0201948 W GB 0201948W WO 03032398 A2 WO03032398 A2 WO 03032398A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transistor
- nanostructure
- channel
- amorphous silicon
- ion
- Prior art date
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 17
- 239000002086 nanomaterial Substances 0.000 claims abstract description 50
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 34
- 150000002500 ions Chemical class 0.000 claims abstract description 32
- -1 nitrogen molecular ions Chemical class 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000007943 implant Substances 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000003989 dielectric material Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 35
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- 230000001131 transforming effect Effects 0.000 abstract 1
- 230000008569 process Effects 0.000 description 16
- 230000037230 mobility Effects 0.000 description 10
- 239000002800 charge carrier Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000010884 ion-beam technique Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 101001051799 Aedes aegypti Molybdenum cofactor sulfurase 3 Proteins 0.000 description 1
- 101710116852 Molybdenum cofactor sulfurase 1 Proteins 0.000 description 1
- 101100537098 Mus musculus Alyref gene Proteins 0.000 description 1
- 101100269674 Mus musculus Alyref2 gene Proteins 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000005535 acoustic phonon Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 101150095908 apex1 gene Proteins 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
Definitions
- the invention relates to methods of forming insulated-gate field-effect transistors (FETs) or MOS-type FETs (MOSFETs) and, in particular, to methods of forming MOS and CMOS field-effect transistors having improved operating characteristics.
- FETs insulated-gate field-effect transistors
- MOSFETs MOS-type FETs
- This device is the main active component of very- large-scale integrated (VLSI) circuits. It occupies the near-surface device region of the semiconductor of a first conductivity type and comprises two high- conductivity (low-ohmic) source and drain regions of a second conductivity type opposite to the first conductivity type and laterally separated by a channel of the device region, which conductivity is controlled by the voltage of the gate electrode positioned above the channel and electrically separated from the channel by gate oxide.
- Minimum of attainable channel length is generally determined by the resolution of lithography methods. At the present time advanced lithography technologies are capable of providing transistor's channel length of less than 100 nm. Consequently, frequencies of about 10 GHz are actually achieved for silicon MOSFETs .
- formula (1) is unsuitable for the evaluation of speed of submicron devices because it does not make allowance for the considerable reduction of mobility ⁇ due to the heating of charge carriers in strong electric field of submicron channels.
- the speed of field- effect transistors and of the device disclosed in [Refl] as well is limited by the capabilities of lithography methods and by the reduction of charge carrier's mobility.
- concentrations' ratio n 2 /n ⁇ >10 and of the number of doping periods in the channel there are provided conditions when electrons drifting in high-ohmic (low-conductivity) nanoregions being not too heated and almost completely giving back the thermal energy acquired in high-ohmic nanoregions (cooling) in low-ohmic (high-conductivity) nanoregions.
- concentrations' ratio n 2 /n ⁇ >10 the concentrations' ratio
- n 2 /n ⁇ >10 the concentrations' ratio n 2 /n ⁇ >10 and of the number of doping periods in the channel, there are provided conditions when electrons drifting in high-ohmic (low-conductivity) nanoregions being not too heated and almost completely giving back the thermal energy acquired in high-ohmic nanoregions (cooling) in low-o
- Refl discloses the MOSFET with n-channel having source-adjoining zone doped by n-type impurity and drain-adjoining zone doped by p-type impurity.
- n-type drain-adjoining zone reduces critical electric field and enhances the breakdown voltage of the drain junction, whereas p-type source-adjoining zone results in more clear subthreshold characteristics.
- the periodical doping of the transistor channel as proposed by the present inventors, enhances the effective electronic mobility and velocity throughout the whole channel and provides in this sense a totally novel solution.
- its implementation in combination with specific doping of source- and drain-adjoining channel zones known from the prior art solutions is also possible.
- a periodically doped channel provides much greater mobility values for charge carriers in the channel because their overall heating is suppressed by periodical cooling in doped (high-conductivity) nanoregions in the channel.
- Formulas (2) correspond to the known theoretical model of electronic scattering by acoustic phonons and their direct use gives the known formula almost precisely describing the effect of saturation of drift velocity v D of electrons in long samples:
- thermorelaxation In case of our interest for overshoot electronic drift in ultra-short-channel, Joule's heating of electrons is much greater than thermorelaxation. For this situation electronic temperature is built up linearly along the transistor channel as
- V is the voltage between transistors' source and drain.
- Formula (4) was deduced in the work involving one of the present inventors (Gergel V. A., Mokerov V. G. , Timofeev M. V., Fedorov Yu. V. "Ultra-quasihydrodynamic electron transport in submicron MOS and hetero field-effect transistors" - Physics and techniques of semiconductors, 2000, torn 34, No. 2, pp. 239-242 [in Russian]) [Ref5] .
- the present inventors estimated a gain resulting from periodical doping of the transistor channel, in which N low-ohmic regions alternating with N high-ohmic regions.
- the frequency f ⁇ characterizing the transistor speed is the same times greater.
- Ref6 discloses the process of periodical doping, which is incompatible with modern VLSI technology of MOS transistors.
- Ref3 does not address the question about the wavelength of the nanostructure to be used as a mask for ion implantation into transistor channel.
- the gain in transconductance and speed of transistor due to periodical doping of their channel cannot be predetermined.
- a method of fabricating field-effect transistor having periodically doped channel comprising: - selecting a wavelength of wave-ordered nanostructure G 2 / 2 times smaller than the length of the transistor channel, G being the desired gain in transistor transconductance and working frequency compared to the transistor not having periodically doped channel, ⁇ being the ratio of the wavelength to the distance between doped regions; - forming a thin layer of screen silicon oxide on the surface of a transistor region of a first conductivity type situated in crystalline silicon; - depositing a layer of amorphous silicon having thickness of one and a half to three depths of nanostructure formation in the amorphous silicon; - sputtering the surface of the amorphous silicon by a flow of nitrogen molecular ions in vacuum so as to form the nanostructure, directing the ion incidence plane along the transistor channel, determining the ion energy, the ion incidence angle to the amorphous silicon surface, the temperature of the amorphous silicon, the formation
- the method includes forming the ion flow of nitrogen molecular ions using Kaufman-type ion source.
- the method includes modifying the nanostructure by reactive ion etching of amorphous silicon in Cl 2 -Ar plasma.
- the invention overcomes the disadvantages of the prior art providing predetermined gain in transconductance and working frequency of a field effect transistor caused by periodical doping of its channel and making the process compatible with conventional VLSI technology.
- FIG. 1 is a cross-sectional view of n-channel MOS transistor region covered by thin screen oxide layer and amorphous silicon layer deposited onto the surface of a silicon wafer.
- FIG. 2 is a cross-sectional view of n-channel MOS transistor region during the process of • 1 nanostructure formation in the amorphous silicon
- FIG. 3 is a cross-sectional view of the
- FIG. 4 is a cross-sectional view of the nanomask.
- FIG. 5 is a cross-sectional view of the nanomask
- FIG. 6 is a cross-sectional view of implants after
- FIG. 7 is a cross-sectional view of n-channel MOS 1 transistor having periodically doped channel.
- FIG. 8 is a perspective view of periodically doped 3 channel and source and drain regions of n-channel 4 MOS transistor. 5 6
- FIG. 1 shows the 7 near-surface region of a p-type silicon wafer 1 with 8 concentration of holes -2-10 17 cm -3 , stop-channel p + - 9 type regions 2, isolation oxide " regions 3, layer of 0 screen oxide 4, and layer 5 of amorphous 1 hydrogenated silicon a-Si:H. Regions 2, 3, and layer 2 4 are formed by known methods of VLSI MOS 3 technology.
- Layer 4 is formed by thermal oxidation 4 of silicon in oxygen atmosphere.
- the thickness of 5 the layer 4 of 15-20 nm is determined by the depth 6 of defects generated by subsequent reactive ion 7 etching and by the selectivity of etching processes 8 of a-Si:H relative to silicon oxide.
- Layer 5 ⁇ 400 nm 9 thick is deposited, as an example, in low-frequency 0 discharge of pure SiH 4 gas for 20 minutes by known 1 method (Budaguan B. G. , Sherchenkov A. A., 2 Struahilev D. A., Sazonov A. Y. , Radosel'sky A. G. , Chernomordic V. D., Popov A. A., and Metselaar J. W.
- FIG. 2 shows the surface of layer 5 irradiated by ion flow 6 of nitrogen molecular ions N 2 + to form the wave-ordered nanostructure.
- Ion gun attached to the vacuum chamber was used to generate the ion beam.
- the nitrogen ion beam of 150 nA current and -10 ⁇ m in diameter was scanned in a raster pattern of 100 by 100 ⁇ m 2 over the area of the layer 5 shown in FIG. 2.
- the wave-ordered nanostructure 7 is formed for ⁇ 2 minutes.
- the initial surface level of the layer 5 lowers due to the sputtering process additionally resulting in the formation of amorphous silicon nitride layer 8 and thin layer of amorphous silicon with nitrogen atoms and N-N pairs 9 on side surfaces of regions 3.
- Required wave-ordered nanostructure shown in FIG. 3 comprises the regions of amorphous silicon nitride 8 and thin layers 9 of amorphous silicon with nitrogen atoms and N-N pairs. As is shown the wave troughs are spaced from the screen oxide 4 at a distance D equal to about one third of the nanostructure wavelength. This arrangement of the nanostructure relative to the layer 4 is achieved through the shutdown of the ion flow 6 at predetermined point of time based on known sputtering rate of layer 5 by the flow of N 2 + ions.
- the wave crests of the nanostructure are arranged perpendicularly to the direction of the ion flow. Therefore the direction of the ion flow is set along the transistor channel as shown by arrows in FIG. 2.
- the process of its modification takes place comprising selective and anisotropic etching of the amorphous silicon layer 5 using regions 8 of the nanostructure as a mask and the layer 4 as a stop-layer for the etching in Cl 2 or Cl 2 -Ar reactive- ion plasma.
- reactive-ion plasma processes are well known and used in up-to-date silicon VLSI technology. (VLSI Electronics Microstructure Science, Volume 8, Plasma Processing for VLSI, Edited by Norman G.
- the peak concentration of implants should be 10 times greater than the dopant concentration on the surface of p transistor region 1, which is ⁇ 2-10 18 cm “3 (with allowance made for the subsequent formation of gate oxide about 10 nm thick) .
- These specified conditions can be met by the implantation of arsenic ions with the energy of 20 keV and the dose of 6-10 12 cm “2 .
- the resulting shallow implants 11 are shown in FIG. 5.
- the nanomask is removed by isotropic etching, as an example, in SF S plasma.
- the layer 4 therewith plays the role of stopping layer again.
- the screen oxide 4 is etched in HF solution.
- the resulting periodically doped structure is that of FIG. 6.
- the distance between the shallow implants (doped regions) 11 along the channel as shown in FIG. 6 is equal to the size of high-ohmic area L H .
- Doping period is equal to the nanostructure wavelength ⁇ .
- the rapid thermal process at 1000°C for 5 minutes sufficient for the formation of 10 nm gate oxide matches this requirement in case of arsenic .
- pMOS can be fabricated with periodically doped channel .
- transistor region is of n-type conductivity and boron ions are implanted into the polysilicon gate, source, and drain regions.
- pMOS and nMOS are complementary and the types of conductivity of their corresponding regions are opposite.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02720273A EP1464086A2 (fr) | 2001-10-09 | 2002-04-26 | Transistor a effet de champ avec canal periodiquement dope |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
RU2001127264/28A RU2191444C1 (ru) | 2001-10-09 | 2001-10-09 | Способ изготовления полевого транзистора с периодически легированным каналом |
RU2001127264 | 2001-10-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003032398A2 true WO2003032398A2 (fr) | 2003-04-17 |
WO2003032398A3 WO2003032398A3 (fr) | 2003-07-03 |
Family
ID=20253616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2002/001948 WO2003032398A2 (fr) | 2001-10-09 | 2002-04-26 | Transistor a effet de champ avec canal periodiquement dope |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1464086A2 (fr) |
RU (1) | RU2191444C1 (fr) |
WO (1) | WO2003032398A2 (fr) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1672415A1 (fr) * | 2004-12-17 | 2006-06-21 | Freewire Limited | Méthode pour former une structure nano-relief sur la surface d'un film |
US20140151715A1 (en) * | 2011-08-05 | 2014-06-05 | Wostec, Inc. | Light emitting diode with nanostructured layer and methods of making and using |
WO2015199573A1 (fr) | 2014-06-26 | 2015-12-30 | Wostec, Inc. | Nanomasque dur de type onde aligné sur une caractéristique topographique ainsi que procédé de fabrication et d'utilisation |
US9500789B2 (en) | 2013-03-13 | 2016-11-22 | Wostec, Inc. | Polarizer based on a nanowire grid |
US9653627B2 (en) | 2012-01-18 | 2017-05-16 | Wostec, Inc. | Arrangements with pyramidal features having at least one nanostructured surface and methods of making and using |
US10672427B2 (en) | 2016-11-18 | 2020-06-02 | Wostec, Inc. | Optical memory devices using a silicon wire grid polarizer and methods of making and using |
US11371134B2 (en) | 2017-02-27 | 2022-06-28 | Wostec, Inc. | Nanowire grid polarizer on a curved surface and methods of making and using |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2754995C1 (ru) * | 2020-11-23 | 2021-09-08 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" | Способ изготовления тонкопленочного транзистора |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4831422A (en) * | 1985-02-13 | 1989-05-16 | Nec Corporation | Field effect transistor |
EP1104011A1 (fr) * | 1999-11-25 | 2001-05-30 | Sceptre Electronics Limited | Procédé de formation de nanostructures en silicium, matrice de fils quantiques et composants basés sur ladite matrice |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5050878A (fr) * | 1973-09-05 | 1975-05-07 |
-
2001
- 2001-10-09 RU RU2001127264/28A patent/RU2191444C1/ru active IP Right Revival
-
2002
- 2002-04-26 WO PCT/GB2002/001948 patent/WO2003032398A2/fr not_active Application Discontinuation
- 2002-04-26 EP EP02720273A patent/EP1464086A2/fr not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4831422A (en) * | 1985-02-13 | 1989-05-16 | Nec Corporation | Field effect transistor |
EP1104011A1 (fr) * | 1999-11-25 | 2001-05-30 | Sceptre Electronics Limited | Procédé de formation de nanostructures en silicium, matrice de fils quantiques et composants basés sur ladite matrice |
Non-Patent Citations (1)
Title |
---|
GERGEL V A ET AL: "ENHANCEMENT OF OPERATION SPEED IN FIELD-EFFECT TRANSISTORS USING CHANNEL PROFILING" DOKLADY AKADEMII NAUK. ROSSIJSKA AKADEMI NAUK, NAUKA, MOSCOW, RU, vol. 375, no. 5, December 2000 (2000-12), pages 609-610, XP001149896 ISSN: 0869-5652 cited in the application * |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1672415A1 (fr) * | 2004-12-17 | 2006-06-21 | Freewire Limited | Méthode pour former une structure nano-relief sur la surface d'un film |
US9660142B2 (en) | 2011-08-05 | 2017-05-23 | Wostec, Inc. | Light emitting diode with nanostructured layer and methods of making and using |
US20140151715A1 (en) * | 2011-08-05 | 2014-06-05 | Wostec, Inc. | Light emitting diode with nanostructured layer and methods of making and using |
US9224918B2 (en) * | 2011-08-05 | 2015-12-29 | Wostec, Inc. 032138/0242 | Light emitting diode with nanostructured layer and methods of making and using |
US9653627B2 (en) | 2012-01-18 | 2017-05-16 | Wostec, Inc. | Arrangements with pyramidal features having at least one nanostructured surface and methods of making and using |
US9500789B2 (en) | 2013-03-13 | 2016-11-22 | Wostec, Inc. | Polarizer based on a nanowire grid |
WO2015199573A1 (fr) | 2014-06-26 | 2015-12-30 | Wostec, Inc. | Nanomasque dur de type onde aligné sur une caractéristique topographique ainsi que procédé de fabrication et d'utilisation |
US20170194167A1 (en) * | 2014-06-26 | 2017-07-06 | Wostec, Inc. | Wavelike hard nanomask on a topographic feature and methods of making and using |
EP3161857A4 (fr) * | 2014-06-26 | 2018-02-14 | Wostec, Inc. | Nanomasque dur de type onde aligné sur une caractéristique topographique ainsi que procédé de fabrication et d'utilisation |
US10879082B2 (en) | 2014-06-26 | 2020-12-29 | Wostec, Inc. | Wavelike hard nanomask on a topographic feature and methods of making and using |
US10672427B2 (en) | 2016-11-18 | 2020-06-02 | Wostec, Inc. | Optical memory devices using a silicon wire grid polarizer and methods of making and using |
US11037595B2 (en) | 2016-11-18 | 2021-06-15 | Wostec, Inc. | Optical memory devices using a silicon wire grid polarizer and methods of making and using |
US11308987B2 (en) | 2016-11-18 | 2022-04-19 | Wostec, Inc. | Optical memory devices using a silicon wire grid polarizer and methods of making and using |
US11371134B2 (en) | 2017-02-27 | 2022-06-28 | Wostec, Inc. | Nanowire grid polarizer on a curved surface and methods of making and using |
Also Published As
Publication number | Publication date |
---|---|
RU2191444C1 (ru) | 2002-10-20 |
WO2003032398A3 (fr) | 2003-07-03 |
EP1464086A2 (fr) | 2004-10-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9735270B2 (en) | Semiconductor transistor having a stressed channel | |
US6096627A (en) | Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of a highly doped amorphous layer as a source for dopant diffusion into SiC | |
US6297104B1 (en) | Methods to produce asymmetric MOSFET devices | |
US6426279B1 (en) | Epitaxial delta doping for retrograde channel profile | |
US6509240B2 (en) | Angle implant process for cellular deep trench sidewall doping | |
KR100401130B1 (ko) | 수직형 채널을 가지는 초미세 mos 트랜지스터 제조방법 | |
US8952391B2 (en) | Silicon carbide semiconductor device and its manufacturing method | |
US7713853B2 (en) | Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices | |
US6331467B1 (en) | Method of manufacturing a trench gate field effect semiconductor device | |
US4810665A (en) | Semiconductor device and method of fabrication | |
US6777745B2 (en) | Symmetric trench MOSFET device and method of making same | |
US4841347A (en) | MOS VLSI device having shallow junctions and method of making same | |
TW200910470A (en) | Enhanced hole mobility p-type JFET and fabrication method therefor | |
US7902030B2 (en) | Manufacturing method for semiconductor device and semiconductor device | |
US20020058385A1 (en) | Semiconductor device and method for manufacturing the same | |
US6887760B2 (en) | Fabrication process of a trench gate power MOS transistor with scaled channel | |
CN111490097A (zh) | 制造功率半导体器件的方法 | |
TWI314753B (en) | Method of manufacturing semiconductor devices | |
US8120058B2 (en) | High-drive current MOSFET | |
WO2003032398A2 (fr) | Transistor a effet de champ avec canal periodiquement dope | |
US20100148251A1 (en) | Semiconductor device and method for manufacturing the same | |
US10439037B2 (en) | Method for manufacturing compound semiconductor device including p-type impurity layer | |
KR101801406B1 (ko) | 반도체 장치 및 관련 제조 방법 | |
GB2074374A (en) | Method of making field effect transistors | |
US7138688B2 (en) | Doping method and semiconductor device fabricated using the method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BY BZ CA CH CN CO CR CU CZ DE DM DZ EC EE ES FI GB GD GE GH HR HU ID IL IN IS JP KE KG KP KR LC LK LR LS LT LU LV MA MD MG MN MW MX MZ NO NZ OM PH PL PT RU SD SE SG SI SK SL TJ TM TN TR TZ UA UG US UZ VN YU ZA ZM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GH GM KE LS MW MZ SD SL SZ UG ZM ZW AM AZ BY KG KZ RU TJ TM AT BE CH CY DE DK FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2002720273 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 2002720273 Country of ref document: EP |
|
NENP | Non-entry into the national phase in: |
Ref country code: JP |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: JP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2002720273 Country of ref document: EP |