EP1464086A2 - Transistor a effet de champ avec canal periodiquement dope - Google Patents

Transistor a effet de champ avec canal periodiquement dope

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Publication number
EP1464086A2
EP1464086A2 EP02720273A EP02720273A EP1464086A2 EP 1464086 A2 EP1464086 A2 EP 1464086A2 EP 02720273 A EP02720273 A EP 02720273A EP 02720273 A EP02720273 A EP 02720273A EP 1464086 A2 EP1464086 A2 EP 1464086A2
Authority
EP
European Patent Office
Prior art keywords
transistor
nanostructure
channel
amorphous silicon
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02720273A
Other languages
German (de)
English (en)
Inventor
Valery Smirnov
Dimitry Kibalov
Victor Gergel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Freewire Ltd
Original Assignee
Freewire Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freewire Ltd filed Critical Freewire Ltd
Publication of EP1464086A2 publication Critical patent/EP1464086A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Definitions

  • the invention relates to methods of forming insulated-gate field-effect transistors (FETs) or MOS-type FETs (MOSFETs) and, in particular, to methods of forming MOS and CMOS field-effect transistors having improved operating characteristics.
  • FETs insulated-gate field-effect transistors
  • MOSFETs MOS-type FETs
  • This device is the main active component of very- large-scale integrated (VLSI) circuits. It occupies the near-surface device region of the semiconductor of a first conductivity type and comprises two high- conductivity (low-ohmic) source and drain regions of a second conductivity type opposite to the first conductivity type and laterally separated by a channel of the device region, which conductivity is controlled by the voltage of the gate electrode positioned above the channel and electrically separated from the channel by gate oxide.
  • Minimum of attainable channel length is generally determined by the resolution of lithography methods. At the present time advanced lithography technologies are capable of providing transistor's channel length of less than 100 nm. Consequently, frequencies of about 10 GHz are actually achieved for silicon MOSFETs .
  • formula (1) is unsuitable for the evaluation of speed of submicron devices because it does not make allowance for the considerable reduction of mobility ⁇ due to the heating of charge carriers in strong electric field of submicron channels.
  • the speed of field- effect transistors and of the device disclosed in [Refl] as well is limited by the capabilities of lithography methods and by the reduction of charge carrier's mobility.
  • concentrations' ratio n 2 /n ⁇ >10 and of the number of doping periods in the channel there are provided conditions when electrons drifting in high-ohmic (low-conductivity) nanoregions being not too heated and almost completely giving back the thermal energy acquired in high-ohmic nanoregions (cooling) in low-ohmic (high-conductivity) nanoregions.
  • concentrations' ratio n 2 /n ⁇ >10 the concentrations' ratio
  • n 2 /n ⁇ >10 the concentrations' ratio n 2 /n ⁇ >10 and of the number of doping periods in the channel, there are provided conditions when electrons drifting in high-ohmic (low-conductivity) nanoregions being not too heated and almost completely giving back the thermal energy acquired in high-ohmic nanoregions (cooling) in low-o
  • Refl discloses the MOSFET with n-channel having source-adjoining zone doped by n-type impurity and drain-adjoining zone doped by p-type impurity.
  • n-type drain-adjoining zone reduces critical electric field and enhances the breakdown voltage of the drain junction, whereas p-type source-adjoining zone results in more clear subthreshold characteristics.
  • the periodical doping of the transistor channel as proposed by the present inventors, enhances the effective electronic mobility and velocity throughout the whole channel and provides in this sense a totally novel solution.
  • its implementation in combination with specific doping of source- and drain-adjoining channel zones known from the prior art solutions is also possible.
  • a periodically doped channel provides much greater mobility values for charge carriers in the channel because their overall heating is suppressed by periodical cooling in doped (high-conductivity) nanoregions in the channel.
  • Formulas (2) correspond to the known theoretical model of electronic scattering by acoustic phonons and their direct use gives the known formula almost precisely describing the effect of saturation of drift velocity v D of electrons in long samples:
  • thermorelaxation In case of our interest for overshoot electronic drift in ultra-short-channel, Joule's heating of electrons is much greater than thermorelaxation. For this situation electronic temperature is built up linearly along the transistor channel as
  • V is the voltage between transistors' source and drain.
  • Formula (4) was deduced in the work involving one of the present inventors (Gergel V. A., Mokerov V. G. , Timofeev M. V., Fedorov Yu. V. "Ultra-quasihydrodynamic electron transport in submicron MOS and hetero field-effect transistors" - Physics and techniques of semiconductors, 2000, torn 34, No. 2, pp. 239-242 [in Russian]) [Ref5] .
  • the present inventors estimated a gain resulting from periodical doping of the transistor channel, in which N low-ohmic regions alternating with N high-ohmic regions.
  • the frequency f ⁇ characterizing the transistor speed is the same times greater.
  • Ref6 discloses the process of periodical doping, which is incompatible with modern VLSI technology of MOS transistors.
  • Ref3 does not address the question about the wavelength of the nanostructure to be used as a mask for ion implantation into transistor channel.
  • the gain in transconductance and speed of transistor due to periodical doping of their channel cannot be predetermined.
  • a method of fabricating field-effect transistor having periodically doped channel comprising: - selecting a wavelength of wave-ordered nanostructure G 2 / 2 times smaller than the length of the transistor channel, G being the desired gain in transistor transconductance and working frequency compared to the transistor not having periodically doped channel, ⁇ being the ratio of the wavelength to the distance between doped regions; - forming a thin layer of screen silicon oxide on the surface of a transistor region of a first conductivity type situated in crystalline silicon; - depositing a layer of amorphous silicon having thickness of one and a half to three depths of nanostructure formation in the amorphous silicon; - sputtering the surface of the amorphous silicon by a flow of nitrogen molecular ions in vacuum so as to form the nanostructure, directing the ion incidence plane along the transistor channel, determining the ion energy, the ion incidence angle to the amorphous silicon surface, the temperature of the amorphous silicon, the formation
  • the method includes forming the ion flow of nitrogen molecular ions using Kaufman-type ion source.
  • the method includes modifying the nanostructure by reactive ion etching of amorphous silicon in Cl 2 -Ar plasma.
  • the invention overcomes the disadvantages of the prior art providing predetermined gain in transconductance and working frequency of a field effect transistor caused by periodical doping of its channel and making the process compatible with conventional VLSI technology.
  • FIG. 1 is a cross-sectional view of n-channel MOS transistor region covered by thin screen oxide layer and amorphous silicon layer deposited onto the surface of a silicon wafer.
  • FIG. 2 is a cross-sectional view of n-channel MOS transistor region during the process of • 1 nanostructure formation in the amorphous silicon
  • FIG. 3 is a cross-sectional view of the
  • FIG. 4 is a cross-sectional view of the nanomask.
  • FIG. 5 is a cross-sectional view of the nanomask
  • FIG. 6 is a cross-sectional view of implants after
  • FIG. 7 is a cross-sectional view of n-channel MOS 1 transistor having periodically doped channel.
  • FIG. 8 is a perspective view of periodically doped 3 channel and source and drain regions of n-channel 4 MOS transistor. 5 6
  • FIG. 1 shows the 7 near-surface region of a p-type silicon wafer 1 with 8 concentration of holes -2-10 17 cm -3 , stop-channel p + - 9 type regions 2, isolation oxide " regions 3, layer of 0 screen oxide 4, and layer 5 of amorphous 1 hydrogenated silicon a-Si:H. Regions 2, 3, and layer 2 4 are formed by known methods of VLSI MOS 3 technology.
  • Layer 4 is formed by thermal oxidation 4 of silicon in oxygen atmosphere.
  • the thickness of 5 the layer 4 of 15-20 nm is determined by the depth 6 of defects generated by subsequent reactive ion 7 etching and by the selectivity of etching processes 8 of a-Si:H relative to silicon oxide.
  • Layer 5 ⁇ 400 nm 9 thick is deposited, as an example, in low-frequency 0 discharge of pure SiH 4 gas for 20 minutes by known 1 method (Budaguan B. G. , Sherchenkov A. A., 2 Struahilev D. A., Sazonov A. Y. , Radosel'sky A. G. , Chernomordic V. D., Popov A. A., and Metselaar J. W.
  • FIG. 2 shows the surface of layer 5 irradiated by ion flow 6 of nitrogen molecular ions N 2 + to form the wave-ordered nanostructure.
  • Ion gun attached to the vacuum chamber was used to generate the ion beam.
  • the nitrogen ion beam of 150 nA current and -10 ⁇ m in diameter was scanned in a raster pattern of 100 by 100 ⁇ m 2 over the area of the layer 5 shown in FIG. 2.
  • the wave-ordered nanostructure 7 is formed for ⁇ 2 minutes.
  • the initial surface level of the layer 5 lowers due to the sputtering process additionally resulting in the formation of amorphous silicon nitride layer 8 and thin layer of amorphous silicon with nitrogen atoms and N-N pairs 9 on side surfaces of regions 3.
  • Required wave-ordered nanostructure shown in FIG. 3 comprises the regions of amorphous silicon nitride 8 and thin layers 9 of amorphous silicon with nitrogen atoms and N-N pairs. As is shown the wave troughs are spaced from the screen oxide 4 at a distance D equal to about one third of the nanostructure wavelength. This arrangement of the nanostructure relative to the layer 4 is achieved through the shutdown of the ion flow 6 at predetermined point of time based on known sputtering rate of layer 5 by the flow of N 2 + ions.
  • the wave crests of the nanostructure are arranged perpendicularly to the direction of the ion flow. Therefore the direction of the ion flow is set along the transistor channel as shown by arrows in FIG. 2.
  • the process of its modification takes place comprising selective and anisotropic etching of the amorphous silicon layer 5 using regions 8 of the nanostructure as a mask and the layer 4 as a stop-layer for the etching in Cl 2 or Cl 2 -Ar reactive- ion plasma.
  • reactive-ion plasma processes are well known and used in up-to-date silicon VLSI technology. (VLSI Electronics Microstructure Science, Volume 8, Plasma Processing for VLSI, Edited by Norman G.
  • the peak concentration of implants should be 10 times greater than the dopant concentration on the surface of p transistor region 1, which is ⁇ 2-10 18 cm “3 (with allowance made for the subsequent formation of gate oxide about 10 nm thick) .
  • These specified conditions can be met by the implantation of arsenic ions with the energy of 20 keV and the dose of 6-10 12 cm “2 .
  • the resulting shallow implants 11 are shown in FIG. 5.
  • the nanomask is removed by isotropic etching, as an example, in SF S plasma.
  • the layer 4 therewith plays the role of stopping layer again.
  • the screen oxide 4 is etched in HF solution.
  • the resulting periodically doped structure is that of FIG. 6.
  • the distance between the shallow implants (doped regions) 11 along the channel as shown in FIG. 6 is equal to the size of high-ohmic area L H .
  • Doping period is equal to the nanostructure wavelength ⁇ .
  • the rapid thermal process at 1000°C for 5 minutes sufficient for the formation of 10 nm gate oxide matches this requirement in case of arsenic .
  • pMOS can be fabricated with periodically doped channel .
  • transistor region is of n-type conductivity and boron ions are implanted into the polysilicon gate, source, and drain regions.
  • pMOS and nMOS are complementary and the types of conductivity of their corresponding regions are opposite.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Cette invention se rapporte à un procédé qui sert à fabriquer un transistor à effet de champ avec canal périodiquement dopé et qui consiste à cet effet à sélectionner une longueur d'onde d'une nanostructure à ordre d'ondes G2/α2 fois inférieure à la longueur du canal du transistor, G représentant le gain souhaité dans la transconductance du transistor et dans la fréquence de travail due au dopage périodique du canal, et α représentant le rapport entre la longueur d'onde et la distance séparant les régions dopées ; à former une mince couche d'oxyde de silicium de criblage sur la surface d'une région de transistor d'un premier type de conductivité, à déposer une couche de silicium amorphe ; à pulvériser sur la surface du silicium amorphe un flux d'ions moléculaires d'azote sous vide, afin de former la nanostructure, à diriger le plan d'incidence des ions le long du canal de transistor, à déterminer l'énergie ionique et l'angle d'incidence des ions sur la surface de silicium amorphe sur la base de la longueur d'onde de la nanostructure ; à transformer la nanostructure en nanomasque par plasma ionique réactif ; à implanter les ions dopants, afin de former dans la région de canal du transistor des implants peu profonds du second type de conductivité identique à celui des régions de source et de drain du transistor et opposé au premier type de conductivité ; à éliminer le nanomasque et l'oxyde de silicium de criblage ; et à former un matériau diélectrique de grille, une grille et des régions de source et de drain pour terminer la fabrication du transistor.
EP02720273A 2001-10-09 2002-04-26 Transistor a effet de champ avec canal periodiquement dope Withdrawn EP1464086A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
RU2001127264 2001-10-09
RU2001127264/28A RU2191444C1 (ru) 2001-10-09 2001-10-09 Способ изготовления полевого транзистора с периодически легированным каналом
PCT/GB2002/001948 WO2003032398A2 (fr) 2001-10-09 2002-04-26 Transistor a effet de champ avec canal periodiquement dope

Publications (1)

Publication Number Publication Date
EP1464086A2 true EP1464086A2 (fr) 2004-10-06

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EP02720273A Withdrawn EP1464086A2 (fr) 2001-10-09 2002-04-26 Transistor a effet de champ avec canal periodiquement dope

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EP (1) EP1464086A2 (fr)
RU (1) RU2191444C1 (fr)
WO (1) WO2003032398A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1672415A1 (fr) * 2004-12-17 2006-06-21 Freewire Limited Méthode pour former une structure nano-relief sur la surface d'un film
WO2013022365A1 (fr) 2011-08-05 2013-02-14 Wostec, Inc. Diode électroluminescente comportant une couche nanostructurée et ses procédés de fabrication et d'utilisation
US9653627B2 (en) 2012-01-18 2017-05-16 Wostec, Inc. Arrangements with pyramidal features having at least one nanostructured surface and methods of making and using
US9500789B2 (en) 2013-03-13 2016-11-22 Wostec, Inc. Polarizer based on a nanowire grid
WO2015199573A1 (fr) 2014-06-26 2015-12-30 Wostec, Inc. Nanomasque dur de type onde aligné sur une caractéristique topographique ainsi que procédé de fabrication et d'utilisation
US10672427B2 (en) 2016-11-18 2020-06-02 Wostec, Inc. Optical memory devices using a silicon wire grid polarizer and methods of making and using
WO2018156042A1 (fr) 2017-02-27 2018-08-30 Wostec, Inc. Polariseur à grille de nanofils sur une surface incurvée et procédés de fabrication et d'utilisation
RU2754995C1 (ru) * 2020-11-23 2021-09-08 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Способ изготовления тонкопленочного транзистора

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Publication number Priority date Publication date Assignee Title
JPS5050878A (fr) * 1973-09-05 1975-05-07
JPS61185973A (ja) * 1985-02-13 1986-08-19 Nec Corp 半導体装置
RU2173003C2 (ru) * 1999-11-25 2001-08-27 Септре Электроникс Лимитед Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств

Non-Patent Citations (1)

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Title
See references of WO03032398A2 *

Also Published As

Publication number Publication date
WO2003032398A3 (fr) 2003-07-03
RU2191444C1 (ru) 2002-10-20
WO2003032398A2 (fr) 2003-04-17

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