EP1464086A2 - Field effect transistor having periodically doped channel - Google Patents

Field effect transistor having periodically doped channel

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Publication number
EP1464086A2
EP1464086A2 EP02720273A EP02720273A EP1464086A2 EP 1464086 A2 EP1464086 A2 EP 1464086A2 EP 02720273 A EP02720273 A EP 02720273A EP 02720273 A EP02720273 A EP 02720273A EP 1464086 A2 EP1464086 A2 EP 1464086A2
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EP
European Patent Office
Prior art keywords
transistor
nanostructure
channel
amorphous silicon
ion
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EP02720273A
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German (de)
French (fr)
Inventor
Valery Smirnov
Dimitry Kibalov
Victor Gergel
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Freewire Ltd
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Freewire Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of fabricating field-effect transistor having periodically doped channel comprising selecting a wavelength of wave-ordered nanostructure G?2/α2¿ times smaller than the length of the transistor channel, G being the desired gain in transistor transconductance and working frequency due to periodical doping of the channel, α being the ratio of the wavelength to the distance between doped regions; forming a thin layer of screen silicon oxide on the surface of a transistor region of a first conductivity type; depositing a layer of amorphous silicon; sputtering the surface of the amorphous silicon by a flow of nitrogen molecular ions in vacuum so as to form the nanostructure, directing the ion incidence plane along the transistor channel, determining the ion energy and the ion incidence angle to the amorphous silicon surface on the basis of the wavelength of the nanostructure; transforming the nanostructure into the nanomask by reactive-ion plasma; implanting the doping ions so as to form in the channel region of the transistor shallow implants of the second conductivity type identical to that for transistor's source and drain regions and opposite to the first conductivity type; removing nanomask and the screen silicon oxide; forming gate dielectric material, a gate, source and drain regions completing the fabrication of the transistor.

Description

Field-effect transistor having periodically doped channel
The invention relates to methods of forming insulated-gate field-effect transistors (FETs) or MOS-type FETs (MOSFETs) and, in particular, to methods of forming MOS and CMOS field-effect transistors having improved operating characteristics.
This device is the main active component of very- large-scale integrated (VLSI) circuits. It occupies the near-surface device region of the semiconductor of a first conductivity type and comprises two high- conductivity (low-ohmic) source and drain regions of a second conductivity type opposite to the first conductivity type and laterally separated by a channel of the device region, which conductivity is controlled by the voltage of the gate electrode positioned above the channel and electrically separated from the channel by gate oxide. Typical examples of up-to-date MOSFET design and technology are presented in the patent specification (Patent US6078082 "Field-Effect Transistor Having Multi-Part Channel" 20.06.2000) [Ref1] . It is known that MOSFET speed or maximal switching frequency fτ in ideal model is inversely proportional to the charge carriers' time of flight τ = L/vD equal to the ratio of. channel length to carriers' drift velocity vD :
i.e. proportional to the carriers' mobility μ in the channel, voltage across the channel V, and inversely proportional to the channel length L squared. (C. M. Sze "Physics of Semiconductor Devices" , Second Edition, 1981, John Wiley and Sons, Inc., Chapter 8) [Ref2] . This has stimulated device designers and technologists to cut transistor's channel length, i.e. the distance between source and drain regions.
Minimum of attainable channel length is generally determined by the resolution of lithography methods. At the present time advanced lithography technologies are capable of providing transistor's channel length of less than 100 nm. Consequently, frequencies of about 10 GHz are actually achieved for silicon MOSFETs .
It should be also noted that formula (1) is unsuitable for the evaluation of speed of submicron devices because it does not make allowance for the considerable reduction of mobility μ due to the heating of charge carriers in strong electric field of submicron channels. Thus, the speed of field- effect transistors and of the device disclosed in [Refl] as well is limited by the capabilities of lithography methods and by the reduction of charge carrier's mobility.
Previously published work involving one of the present inventors discloses the idea of enhancing the speed of field-effect transistors due to the increase in charge carrier's mobility (V. A. Gergel, V. G. Mokerov "About the enhancement of the speed of field-effect transistors due to profiling the channel" - Dokladi Akademii Nauk, 2000, torn 375, No. 5, pp. 609-610 [in Russian]) [Ref3] , which was aimed at the suppression of the negative influence of heating of charge carriers in the channel on transistor operating characteristics and consists in the formation of alternating nanoregions with high and low conductivity extended across the channel. The electric field in the channel of such a transistor will oscillate as the ratio of conductivities (concentrations of charge carriers) in adjacent nanoregions Eι/E2=n2/n!. On a proper choice both of concentrations' ratio n2/nι>10 and of the number of doping periods in the channel, there are provided conditions when electrons drifting in high-ohmic (low-conductivity) nanoregions being not too heated and almost completely giving back the thermal energy acquired in high-ohmic nanoregions (cooling) in low-ohmic (high-conductivity) nanoregions. By doing so, along the channel with doping nanoregions average electronic temperature is kept rather low, enabling high electronic mobility μ=μo as for low electric field conditions.
However, the idea to form a channel having doped nanoregions as disclosed in Ref3 is insufficient for practical realization. In Ref3 mention is only made of the fact that this formation can be based on methods for self-formation of nanostructures .
At present time there are examples of practical implementation of the idea of partitioning the MOSFET' s channel. In particular, Refl discloses the MOSFET with n-channel having source-adjoining zone doped by n-type impurity and drain-adjoining zone doped by p-type impurity. In this design n-type drain-adjoining zone reduces critical electric field and enhances the breakdown voltage of the drain junction, whereas p-type source-adjoining zone results in more clear subthreshold characteristics. The periodical doping of the transistor channel, as proposed by the present inventors, enhances the effective electronic mobility and velocity throughout the whole channel and provides in this sense a totally novel solution. However its implementation in combination with specific doping of source- and drain-adjoining channel zones known from the prior art solutions is also possible.
A periodically doped channel, as shown below by the present inventors, provides much greater mobility values for charge carriers in the channel because their overall heating is suppressed by periodical cooling in doped (high-conductivity) nanoregions in the channel.
The evaluation of the gain resulting from periodical doping of the transistor channel is given below from the point of using the effect at room temperature T0. Hereinafter temperature is measured in volts proportionally to its value in kelvins, in this case T0=300K~0, 026V. In addition, used here is the known simplest model of the dependence of kinetic factors on electronic temperature :
where electronic mobility μ0=μ (T0) =1, 5-103 cm2/ (V-s) and energy relaxation time τ0=τ (T0) = 5-10'13 s. Formulas (2) are given in the book (B. K. Ridley "Quantum processes in semiconductors" , Second edition, Oxford University Press, Inc., 1982, 286 pp. ) [Ref4] .
Formulas (2) correspond to the known theoretical model of electronic scattering by acoustic phonons and their direct use gives the known formula almost precisely describing the effect of saturation of drift velocity vD of electrons in long samples:
where E is the electric field in the transistor channel, vs is the saturated drift velocity in accordance with Ref4. In this traditional situation steady-state electronic temperature T=ΪO+μ0τ0 2 is established as a result of balance between Joule's heating of electrons in the electric field and their "cooling" (thermorelaxation) by losing excess thermal energy to the lattice through emitting the appropriate number of phonons .
In case of our interest for overshoot electronic drift in ultra-short-channel, Joule's heating of electrons is much greater than thermorelaxation. For this situation electronic temperature is built up linearly along the transistor channel as
2 T = T0 +-V, (4)
5 where V is the voltage between transistors' source and drain. Formula (4) was deduced in the work involving one of the present inventors (Gergel V. A., Mokerov V. G. , Timofeev M. V., Fedorov Yu. V. "Ultra-quasihydrodynamic electron transport in submicron MOS and hetero field-effect transistors" - Physics and techniques of semiconductors, 2000, torn 34, No. 2, pp. 239-242 [in Russian]) [Ref5] . The present inventors deduced the important criterion establishing a line of demarcation between usual and overshoot modes of electronic drift : for overshoot electronic drift heating without regard to heat losses 2V/5 should be less than steady-state heating μ0Xo 2 , which with V/L in place of E can be written as μ0τo 2 U < 2 > — (5) 5 From the formula (5) it follows that the modern MOS field-effect transistor with typical submicron channel of 0, 25 μm at a drain voltage of IV is already under the condition of overshoot mode. On the basis of formulas (1) , (2) , and (4) the present inventors estimated the average electronic velocity in the transistor channel as:
. For the transistor with L = 0,25 μm at V = IV the drift velocity vD is more than twice as great as the velocity of saturation vs.
Using formula (6) the present inventors estimated a gain resulting from periodical doping of the transistor channel, in which N low-ohmic regions alternating with N high-ohmic regions.
For this in (6) instead of V it is necessary to substitute V/N, and instead of L - L/ (aN) , where α is the geometry factor α=λ/LH equal to the ratio of doping period λ to the size of high-ohmic area LH. It turns out that carriers' velocity and, hence, transconductance of the transistor having periodically doped channel are G= v/V times greater than carriers' velocity and transconductance of the conventional transistor with the same channel length. The absolute value of electron velocity is on the order of magnitude greater than typical value of 107 cm/s reaching 20s cm/s .
Correspondingly, the frequency fτ characterizing the transistor speed is the same times greater.
It is possible to differently formulate the advantages of the proposed transistor having partitioned channel. The electrical properties of the transistor with the partitioned channel of length L are equivalent to the properties of prior art transistor with distance from source to drain G=αvΛ/ times smaller. Thus, multiplication of both transconductance and working frequency of silicon MOS field-effect transistor by the factor of G requires a periodical doping of the channel with the period that N-G2/ 2 times smaller than the channel length L (for α=2 N=G2/4 , for α=2,7 N=G2/3 ) . United States Patent, inventors of which are among the present inventors, discloses the method of formation of a silicon wave-ordered nanostructure (US6274007 Methods of formation of a silicon nanostructure, a silicon quantum wire array, and devices based thereon 14.08.2001) [Ref6] . This nanostructure can be used as a mask for ion implantation to periodically dope the nanostructure itself. However Ref6 does not disclose the process compatible with currently available VLSI MOS technology to periodically dope the transistor channel. The above mentioned references Ref3 and Ref6 in combination disclose a basic method for the formation of field-effect transistor having periodically doped channel. But enhanced charge carriers' mobility in the channel cannot be achieved by this basic method because Ref6 discloses the process of periodical doping, which is incompatible with modern VLSI technology of MOS transistors. In addition, Ref3 does not address the question about the wavelength of the nanostructure to be used as a mask for ion implantation into transistor channel. Thus, the gain in transconductance and speed of transistor due to periodical doping of their channel cannot be predetermined.
Present inventors, after further investigation of the nanostructure formation process on the surface of amorphous silicon a-Si depending on incidence angle θ and the energy of nitrogen ions E have found that the dependences of nanostructure formation depth DF and its wavelength λ on angle θ and energy E behave in a manner like the dependencies disclosed in Ref6 for monocrystalline silicon c-Si. Compared to c-Si, layers of a-Si can be easily deposited as auxiliary layers by high throughput methods of VLSI technology.
In accordance with the invention, there is provided a method of fabricating field-effect transistor having periodically doped channel, comprising: - selecting a wavelength of wave-ordered nanostructure G2/ 2 times smaller than the length of the transistor channel, G being the desired gain in transistor transconductance and working frequency compared to the transistor not having periodically doped channel, α being the ratio of the wavelength to the distance between doped regions; - forming a thin layer of screen silicon oxide on the surface of a transistor region of a first conductivity type situated in crystalline silicon; - depositing a layer of amorphous silicon having thickness of one and a half to three depths of nanostructure formation in the amorphous silicon; - sputtering the surface of the amorphous silicon by a flow of nitrogen molecular ions in vacuum so as to form the nanostructure, directing the ion incidence plane along the transistor channel, determining the ion energy, the ion incidence angle to the amorphous silicon surface, the temperature of the amorphous silicon, the formation depth of the nanostructure and the height of the nanostructure, all on the basis of the selected wavelength of the nanostructure, until nanostructure wave troughs being at a distance from the screen oxide of about one third of the selected wavelength; - modifying the nanostructure by removing the amorphous silicon selectively with respect to silicon nitride and silicon oxide vertically about and down to the surface of the screen oxide; - implanting the doping ions so as to form in the channel region of the transistor shallow implants of the second conductivity type identical to that for transistor's source and drain regions and opposite to the first conductivity type; - removing modified nanostructure isotropically and selectively with respect to silicon oxide; - removing the screen silicon oxide selectively with respect to silicon; - forming gate dielectric material, a gate, source and drain regions .
Preferably, the method includes forming the ion flow of nitrogen molecular ions using Kaufman-type ion source. Preferably, the method includes modifying the nanostructure by reactive ion etching of amorphous silicon in Cl2-Ar plasma.
The invention overcomes the disadvantages of the prior art providing predetermined gain in transconductance and working frequency of a field effect transistor caused by periodical doping of its channel and making the process compatible with conventional VLSI technology.
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: FIG. 1 is a cross-sectional view of n-channel MOS transistor region covered by thin screen oxide layer and amorphous silicon layer deposited onto the surface of a silicon wafer. FIG. 2 is a cross-sectional view of n-channel MOS transistor region during the process of •1 nanostructure formation in the amorphous silicon
2 layer on the surface of a silicon wafer.
3 FIG. 3 is a cross-sectional view of the
4 nanostructure in the amorphous silicon layer.
5 FIG. 4 is a cross-sectional view of the nanomask.
6 FIG. 5 is a cross-sectional view of the nanomask
7 during the process of ion implantation.
8 FIG. 6 is a cross-sectional view of implants after
9 . the removal of the nanomask and screen oxide layer. 0 FIG. 7 is a cross-sectional view of n-channel MOS 1 transistor having periodically doped channel. 2 FIG. 8 is a perspective view of periodically doped 3 channel and source and drain regions of n-channel 4 MOS transistor. 5 6 Referring now to the drawings, FIG. 1 shows the 7 near-surface region of a p-type silicon wafer 1 with 8 concentration of holes -2-1017 cm-3, stop-channel p+- 9 type regions 2, isolation oxide" regions 3, layer of 0 screen oxide 4, and layer 5 of amorphous 1 hydrogenated silicon a-Si:H. Regions 2, 3, and layer 2 4 are formed by known methods of VLSI MOS 3 technology. Layer 4 is formed by thermal oxidation 4 of silicon in oxygen atmosphere. The thickness of 5 the layer 4 of 15-20 nm is determined by the depth 6 of defects generated by subsequent reactive ion 7 etching and by the selectivity of etching processes 8 of a-Si:H relative to silicon oxide. Layer 5 ~400 nm 9 thick is deposited, as an example, in low-frequency 0 discharge of pure SiH4 gas for 20 minutes by known 1 method (Budaguan B. G. , Sherchenkov A. A., 2 Struahilev D. A., Sazonov A. Y. , Radosel'sky A. G. , Chernomordic V. D., Popov A. A., and Metselaar J. W. "Amorphous Hydrogenated Silicon Films for Solar Cell Application Obtained with 55 kHz Plasma Enhanced Chemical Vapor Deposition" - Journal of the Electrochemical Society, 1998, Vol. 145, No 7, p. 2508-2512) [Ref7] . There are at least two additional known methods to form amorphous silicon layer. One is the low pressure chemical vapor deposition at 550°C. The other is the vapor deposition through the evaporation of silicon by electron beam in high vacuum. In this relation an important point is that the required nanostructure can be grown on an amorphous silicon layer deposited by any one of mentioned above methods.
FIG. 2 shows the surface of layer 5 irradiated by ion flow 6 of nitrogen molecular ions N2 + to form the wave-ordered nanostructure. Nanostructure wavelength λ=150 nm corresponds to the angle of ion incidence referred to the surface normal of the layer 5 of 45°, ion energy of 8 keV, and nanostructure formation depth DF = 120 nm at room temperature of the sample. Ion gun attached to the vacuum chamber was used to generate the ion beam. The nitrogen ion beam of 150 nA current and -10 μm in diameter was scanned in a raster pattern of 100 by 100 μm2 over the area of the layer 5 shown in FIG. 2. As a result the wave-ordered nanostructure 7 is formed for ~2 minutes. Therewith the initial surface level of the layer 5 lowers due to the sputtering process additionally resulting in the formation of amorphous silicon nitride layer 8 and thin layer of amorphous silicon with nitrogen atoms and N-N pairs 9 on side surfaces of regions 3.
To raise the productivity of nanostructure formation process it is reasonable to use Kaufman-type ion source enabling the creation of wide ion beams and for the energy of N2 + ions greater than 1 keV providing 1 mA-cm"2 ion current density, which is almost equal to the ion current distributed over the raster 1,5 mA-cm-2 for the ion gun used. Wide ion beam can process the whole wafer simultaneously for ~2 minutes. Vacuum setup equipped with Kaufman-type ion source should be designed so that the incidence angle of the ion beam to the wafer surface normal can be varied in the range 40 to 60° by tilting the wafer holder.
Required wave-ordered nanostructure shown in FIG. 3 comprises the regions of amorphous silicon nitride 8 and thin layers 9 of amorphous silicon with nitrogen atoms and N-N pairs. As is shown the wave troughs are spaced from the screen oxide 4 at a distance D equal to about one third of the nanostructure wavelength. This arrangement of the nanostructure relative to the layer 4 is achieved through the shutdown of the ion flow 6 at predetermined point of time based on known sputtering rate of layer 5 by the flow of N2 + ions.
The wave crests of the nanostructure are arranged perpendicularly to the direction of the ion flow. Therefore the direction of the ion flow is set along the transistor channel as shown by arrows in FIG. 2. After the formation of the wave-ordered nanostructure the process of its modification takes place comprising selective and anisotropic etching of the amorphous silicon layer 5 using regions 8 of the nanostructure as a mask and the layer 4 as a stop-layer for the etching in Cl2 or Cl2-Ar reactive- ion plasma. Such reactive-ion plasma processes are well known and used in up-to-date silicon VLSI technology. (VLSI Electronics Microstructure Science, Volume 8, Plasma Processing for VLSI, Edited by Norman G. Einspruch and Dale M. Brown Academic Press, Inc., 1984) [Ref8] . As a result the nanostructure transforms into the nanomask shown in FIG. 4. Regions of amorphous silicon 5 covered by the regions of silicon nitride 8 remain on the surface of screen oxide layer 4.
For high selectivity of reactive-ion plasma etching of amorphous silicon relative to silicon nitride there is the need for removing thin layers 9, as an example, in HF solution highly diluted by HN03 prior the modification of the nanostructure in the plasma. The subsequent process of implantation of arsenic ions using the nanomask is shown in FIG. 5. Regions 5 and 8 of the nanomask and layer 4 prevent arsenic ions 10 from being implanted into p transistor region 1. The in-depth profile of implanted ions should be peaked on the surface of p transistor region 1 (at the lower boundary of the screen oxide 4) . The peak concentration of implants should be 10 times greater than the dopant concentration on the surface of p transistor region 1, which is ~2-1018 cm"3 (with allowance made for the subsequent formation of gate oxide about 10 nm thick) . These specified conditions can be met by the implantation of arsenic ions with the energy of 20 keV and the dose of 6-1012 cm"2. The resulting shallow implants 11 are shown in FIG. 5.
After the ion implantation the nanomask is removed by isotropic etching, as an example, in SFS plasma. The layer 4 therewith plays the role of stopping layer again. Thereupon the screen oxide 4 is etched in HF solution.
The resulting periodically doped structure is that of FIG. 6. The distance between the shallow implants (doped regions) 11 along the channel as shown in FIG. 6 is equal to the size of high-ohmic area LH. Doping period is equal to the nanostructure wavelength λ. In the presented example the geometry factor is evaluated as α=λ/LH=l,7. Suppose the desired gain G=5 in transistor transconductance and working frequency compared to the transistor not having periodically doped channel and the channel length of the transistor L=l,3 μm. In accordance with the invention the nanostructure wavelength was selected as λ=L/(G2/α2) = 150 nm.
The formation of gate oxide 12, polysilicon gate 13, the implantation ,of arsenic ions into the gate 13, source 14, and drain regions 15, the activation of implanted dopants using rapid thermal annealing, the deposition of low-temperature dielectric (not shown) on top of the structure, the thermal planarization of the dielectric surface, metallization (not shown) , and passivation are performed to complete the fabrication of the transistor shown in FIGS. 7 and 8. It is important to use therewith the thermal processes not extending the shape of implants 11 due to diffusion. The rapid thermal process at 1000°C for 5 minutes sufficient for the formation of 10 nm gate oxide matches this requirement in case of arsenic .
Similarly, pMOS can be fabricated with periodically doped channel . In this case transistor region is of n-type conductivity and boron ions are implanted into the polysilicon gate, source, and drain regions. Thus, pMOS and nMOS are complementary and the types of conductivity of their corresponding regions are opposite.
The difference of electron and hole mobilities (μn/μp=2,5) in CMOS integrated circuits (ICs) is compensated for by the extending of the channel width of pMOS transistors. Enhancing the transconductance of only pMOS transistors by a factor of μn/μp due to periodical doping of their channels makes both the transconductances of complementary pMOS and nMOS transistors and their sizes equal thus rising the speed and integration of CMOS ICs. Preferably periodical doping of channels of pMOS and nMOS transistors in CMOS ICs is performed with different doping periods λp/λπ= μn/μp »2, 6 providing equal transconductances and the sizes of complementary pMOS and nMOS transistors. The gain in transconductances for pMOS and nMOS transistors therewith obeys the ratio Gp/Gn=μn/μp .
Improvements and modifications may be incorporated without departing from the scope of the invention as defined in the claims appended hereto.

Claims

1 Claims
2 1. A method of fabricating field-effect transistor
3 having periodically doped channel, comprising:
4 selecting a wavelength of wave-ordered nanostructure
5 G2/ 2 times smaller than the length of the
6 transistor channel, G being the desired gain in
7 transistor transconductance and working frequency
8 compared to the transistor not having
9 periodically doped channel, α being the ratio of
10 the wavelength to the distance between doped
11 regions;
12 forming a thin layer of screen silicon oxide on the
13 surface of a transistor region of a first
14 conductivity type situated in crystalline
15 silicon;
16 depositing a layer of amorphous silicon having
17 thickness of one and a half to three depths of
18 nanostructure formation in the amorphous silicon;
19 sputtering the surface of the amorphous silicon by a 20. flow of nitrogen molecular ions in vacuum so as
21 to form the nanostructure, directing the ion
22 incidence plane along the transistor channel,
23 determining the ion energy, the ion incidence
24 angle to the amorphous silicon surface, the
25 temperature of the amorphous silicon, the
26 formation depth of the nanostructure and the
27 height of the nanostructure, all on the basis of
28 the selected wavelength of the nanostructure,
29 until nanostructure wave troughs being at a
30 distance from the screen oxide of about one third
31 of the selected wavelength; modifying the nanostructure by removing the amorphous silicon selectively with respect to silicon nitride and silicon oxide vertically about and down to the surface of the screen oxide ; implanting the doping ions so as to form in the channel region of the transistor shallow implants of the second conductivity type identical to that for transistor's source and drain regions and opposite to the first conductivity type; removing modified nanostructure isotropically and selectively with respect to silicon oxide; removing the screen silicon oxide selectively with respect to silicon; forming gate dielectric material, a gate, source and drain regions. 2. A method as claimed in claim 1, wherein the ion flow of nitrogen molecular ions is formed using Kaufman-type ion source. 3. A method as claimed in claim 1, wherein the nanostructure is modified by reactive ion etching of amorphous silicon in Cl2-Ar plasma. 4. A field-effect transistor fabricated in accordance with any one of claims 1 - 3.
EP02720273A 2001-10-09 2002-04-26 Field effect transistor having periodically doped channel Withdrawn EP1464086A2 (en)

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RU2001127264 2001-10-09
RU2001127264/28A RU2191444C1 (en) 2001-10-09 2001-10-09 Method for manufacturing field-effect transistor with periodically doped channel
PCT/GB2002/001948 WO2003032398A2 (en) 2001-10-09 2002-04-26 Field effect transistor having periodically doped channel

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EP1672415A1 (en) * 2004-12-17 2006-06-21 Freewire Limited Method of forming a nanorelief structure on a film surface
JP5840294B2 (en) 2011-08-05 2016-01-06 ウォステック・インコーポレイテッドＷｏｓｔｅｃ， Ｉｎｃ LIGHT EMITTING DIODE HAVING NANOSTRUCTURE LAYER, MANUFACTURING METHOD AND USING METHOD
WO2013109157A1 (en) 2012-01-18 2013-07-25 Wostec, Inc. Arrangements with pyramidal features having at least one nanostructured surface and methods of making and using
US9500789B2 (en) 2013-03-13 2016-11-22 Wostec, Inc. Polarizer based on a nanowire grid
US20170194167A1 (en) 2014-06-26 2017-07-06 Wostec, Inc. Wavelike hard nanomask on a topographic feature and methods of making and using
WO2018093284A1 (en) 2016-11-18 2018-05-24 Wostec, Inc. Optical memory devices using a silicon wire grid polarizer and methods of making and using
WO2018156042A1 (en) 2017-02-27 2018-08-30 Wostec, Inc. Nanowire grid polarizer on a curved surface and methods of making and using
RU2754995C1 (en) * 2020-11-23 2021-09-08 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Method for manufacturing a thin-film transistor

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