RU1774325C - Framing word discriminator - Google Patents

Abstract

The invention relates to automation, can be used in digital information transmission systems to synchronize the reception of a continuous digital stream, divided into information frames, and is an improvement of the invention by the author. St. No. 1704146. The aim of the invention is to reduce the time to restore synchronism. An apparatus for extracting a frame sync word in addition to the main device includes a trigger, a binary counter, single vibrators, a delay element, OR elements. The proposed device provides zeroing the cells of the random access memory block after the first detection of KSS, which eliminates the likelihood of a false operation of the device after short-term interruptions in frame synchronization and thereby reduces the synchronization recovery time.

Description

The invention relates to automation, can be used in digital information transmission systems to synchronize the reception of a continuous digital stream, divided into information frames, and is an improvement of the invention by the author. St. No. 1704146.

The aim of the invention is to reduce synchronization restoration time.

The drawing shows a structural diagram of the device.

A device for extracting a frame sync word contains a control unit 1, code converter 2, address generator 3, random access memory block 4, a reverse counter 5, a read-only memory block 6, a first comparison unit 7, a first trigger 8, a frequency divider 9, a counter 10 frame format, frame synchronization word generator (FCC) 11, second comparison unit 12, error counter 13 side, single vibrators 14, 15, delay element 16, second trigger 17, binary counter 18, first OR element 19, third single vibrator 20, second element OR 21, fourth single vibrator 22.

In the initial state, in the absence of an input digital stream, a binary code is present at the outputs of the code converter 2, corresponding to the period of occurrence of the KCC element among the elements of the digital stream. The trigger 8 is in the state of log.1 at its inverse output, which blocks the operation of the frame format counter 10 and the KCC generator 11. Trigger 17 is in a log state. 1 at its inverse output and blocks the operation of the binary counter 18. At the outputs of the one-shots 14, 15, 20. 22, there are log potentials. ABOUT.

An apparatus for extracting a frame sync word operates as follows.

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At the inputs of the Converter 2 receives the code bit rate (DI) or, which is the same thing, the code structure of the cycle. Converter 2 converts the received input information into a preset code, which is fed to the inputs of address generator 3 and divider 9. Address generator 3 at its outputs sequentially generates address codes, the number of which is equal to the multiplicity of the frequency of repetition of the KSS frequency of occurrence of the symbols of the digital signal. In the initial state, after turning on the supply voltage, block 4 is reset (the zeroing scheme is not shown in the drawing), the operation of control unit 1 is to generate two signals at the input of the device of an information symbol (digital sequence element) providing control over the operation of blocks 4 and 5. The clock signal f 1 passes to the output of the control block 1, thereby generating a preset signal for the address generator 5. Following the clock cycle fi, the clock signal fa forms a recording signal in block 4.

The operation of the address generator 3 is to generate an address for block 4 upon the appearance of each subsequent clock signal accompanying the information symbol. A binary counter is used as the main element of the address generator 3, the output code of which is the address of block 4. Upon arrival of the clock pulse, the state of the binary counter changes and, accordingly, the address of block 4 changes. The address generator 3 generates a predetermined number of addresses corresponding to the minimum number of information symbols tins located between the KCC symbols, i.e., a linearly varying binary code is present at the counter output. After the last address has been generated, the address generator 3 returns to its original state and its cycle is repeated, i.e. it works cyclically in the search process KCC.

In accordance with the NA address, at the output of block 4, a binary NC code appears (at the first moment of time it is zero), which corresponds to the number of matches of the KSS code with the elements of the digital signal. This code is the preset code of the reverse counter 5, which generates the address codes of the unit 6 storing the reference CCC.

The receipt of digital information at the input of the device is accompanied by the clock signals Tm and T3, shifted relative to Ti by half the period.

The cycle of work in the search for KSS does not exceed the duration of the period of the clock signal. In each cycle of operation with the arrival of a clock signal, Ti changes NA, by

at the same time, the output of block 4 displays an NC code, which, according to the signal of control unit 1, is rewritten into a reversible counter 5. At the output of block 6, the corresponding element of CCC appears. In block 7 of the comparison, the elements of the reference SSC and digital information are compared. According to the decline of the clock signal Ti at the outputs of the unit 7 comparison appears signal coincidence (mismatch), which passes on

5 counting input (or reset output via OR element 21) of address generator 5. The NB code from the output of the reversible counter 5 is fed to the data inputs of block 4 and is transferred to the block by the signal of control block 1

0 4. Shaper 3 addresses works cyclically, the length of its cycle with n Ti. The reverse counter 5 in each cycle of the device operation generates an address (the number of the KCC element) depending on the results of comparison in the previous and current cycles.

After a number of cycles of operation of the device, in the cell of unit 4 with the NAI address, an NCI code equal to Nci k-1 appears

0 where k is the number of elements of the CSS.

If in block 7, the comparison in the current cycle of the last KSS element with the QI element coincides, the next clock cycle passes to the counting input of the reverse counter 5

5 pulse, which causes its overflow and leads to the appearance on its output of the overflow signal log.1. With this signal, trigger 8 is switched to a single state. Reverse overflow

0 counter 5 indicates that the KCC code is detected in the digital code. After that, the device goes into synch mode,

In this mode, the phased divider 9 generates signals at its output with a frequency proportional to the frequency of the occurrence of the KSS. The frame format counter 10 counts the length of the frame, and in the process of this counting, at the outputs of block 11, a KCC code appears, which is element-wise compared with the KCC code received in the digital signal, a. the comparison result is gated by the output of the delay element 16,

If the number of mismatches calculated by the error counter 13 exceeds a certain threshold value, the output of the counter 13 is a signal that triggers the one-shot 24, the output of which trigger 6 switches to the zero state. The device goes over

to the CSR search mode, If the number of mismatches does not exceed the threshold value, at the end of the frame length count, the output of the counter 10 shows a signal that starts the one-shot 15, The output of the one-shot 15 is a frame synchronization signal.

After the BCC is detected by the overflow signal of the reverse counter 5, the trigger 17 switches to the log state. 1 at its direct output, and a single-vibrator 22 is started, which phases the address driver 3 with its signal. The counter 18 begins the countdown of the interval until the beginning of the next KSS, after which the signal overflows the binary counter 18 through the element IL 19 and starts the single vibrator 20, with its output signal resetting the trigger 17 and the binary counter 18. During the operation of the binary counter 18, the trigger 17 signal the log. 1, from the direct output through the OR element 21, keeps the reversible counter 5 in the zero state. Thus, after the detection of KSS and the transition of the device to the synchronization mode, zero information is entered into the cells of the RAM block 4, i.e., the cells of the block 4 are cleared in the interval by two neighboring KSS.

Since, after the frame duration expires, the RAM block 4 is brought to the zero state, sro allows you to start the search for KSS without taking into account the results accumulated in the previous search cycle. This eliminates the risk of false overflow.

a reversible counter 5 and thereby reduces the synchronization time.

Claims (1)

SUMMARY OF THE INVENTION A device for highlighting a frame sync word by auth. St. N; 1704146, characterized in that, in order to reduce the synchronization recovery time, a second trigger, a binary counter, the first and second OR elements, the third and fourth single-vibrators and a delay element connected between the output of the frequency divider and the second input of the second comparison unit are introduced into it wherein the overflow output of the reverse counter is connected to the installation input of the address generator through the third one-shot and to the single input of the second trigger, the inverse output of which is connected to the resolution input of the binary counter ka, the overflow output of which is connected to the first input of the first OR element, the output of which through the fourth single-vibrator is connected to the inputs of the installation of the second trigger and the binary counter, the clock input of the binary counter is connected to the output of the frequency divider, the output of the second one-shot is connected to the second input of the first element OR, the first output of the first comparison unit is connected to the first input of the OR element, the second input of which is connected to the direct output of the second trigger, the output of the second OR element is connected to the output of the unit down counter.