SU1363490A1 - Adaptive regenerator - Google Patents

Abstract

The invention relates to communication technology, in particular to a digital signal recovery device. The aim of the invention is to improve the noise immunity of the regenerator. To achieve the goal, the device includes grs pulses 25, control unit 10, counters 23, 17, signal advance detection unit 13, RS trigger 22, counting trigger 20, element OR 19, signal delay detection unit 15, element block OR 14, two decoders 16, 21, drive 18, comparison unit 24, two pulse makers 6.7, two pulse recovery units 11, 12, pulse detection unit 9. By increasing the noise level in the line, the regenerator responds by reducing the inertia of its synchronization circuits. As a result, the correlation between information pulses and clock sync pulses increases. As a result, the probability of errors is reduced when the digital signal is restored in the regenerator. The simultaneous use of two methods for detecting information pulses allows one to successfully reconstruct signals that are prone to edge distortion and fragmentation. This contributes to an even greater increase in the fidelity of the transmitted information. 5,1 Il CL co o co 4 ;: CO fig /

Description

The invention relates to communication technology, in particular to digital signal recovery devices.

The purpose of the invention is to increase the noise immunity of the regenerator.

Fig. 1 shows a block diagram of an adaptive regenerator j in FIG. 2, time diagrams of its operation; Fig. 3 illustrates the implementation of a pulse detection unit; Fig. 4 illustrates the implementation of a pulse recovery unit; in fig. 5 is a diagram of the implementation of the control unit; Fig. 6 illustrates the implementation of a signal detection unit; FIG. 7 is a schematic diagram of the implementation of the signal delay detection unit in FIG. 8 is a diagram of the implementation of the comparison unit;

An ad-hoc regenerator consists of an adjustable artificial line 1, a correction amplifier 2, an automatic gain control unit 3, a separation unit 4, an output pulse generator 5, a first pulse former 6, a second pulse former 7, a first pulse detection unit 8 , the control unit 10, the first pulse recovery unit 11, the second pulse recovery unit 12, the signal advance detection unit 13, the OR element block 14, the 15 block

counter 17, accumulator 18, element OR 19, counting trigger 20, second decryptor 21, RS flip-flop 22, first counter 23, comparison unit 24, pulse generator 25.

Adaptive regenerator works as follows.

A pulse signal comes from the communication line to the input of the regenerator, which has quite significant distortions and on which various interferences are superimposed (FIG. 2a). As the conditions of their passage along the communication line are changed by the blocks 3 of the automatic gain control and the adjustable artificial line 1, Since the digital signal is quasi-trenched, it is necessary to restore separately resilient

detecting the lag time of I, first decoder 16, second

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and negative impulses. The signal at the first output of separation unit 4 represents the positive pulses of a linear sequence, and the signal at the second output of separation unit 4 represents the inverted negative pulses of a linear sequence (Figs. 2c, d). The passage through the first 6 and second 7 pulse shapers, which have trigger thresholds at the level of half the amplitude of the pulse, the sequence of pulses acquires a straight coal shape (FIG. 2d),

The signals from the outputs of the first 6 and second 7 pulse formers are supplied to the first 8 and second 9 pulse detection units, respectively. The first clock inputs of these blocks receive square clock pulses from the second (direct) output of the counting trigger 20 (FIG. 2m). The second synchronous clock inputs of blocks 8 and 9 of pulse detection are given by square pulses from pulse generator 25 (FIG. 2k) The frequency of these pulses is chosen such that during the duration of one undistorted information pulse η 50-100 periods of the high-frequency signal would fit, In this regenerator n is equal to 50,

Detection of pulses in BOI blocks is performed simultaneously by the method of alignment and the method of integration. The appearance is short: they fluctuate in phase pulses at the output of blocks 8 and 9 of the pulse detection corresponds to the detection of units (FIG. 2e). These short pulses from the outputs of blocks 8 and 9 pulse detections are then fed to the inputs of the first and second blocks

11 and 12 pulse recovery.

The first clock inputs of these blocks are supplied with clock pulses from the first (inverse) output of the counting trigger 20 (FIG. 2n), and the second clock inputs of these blocks are fed with clock pulses from the second (direct) output CT (FIG. 2m),

The recovered information pulses from the first outputs of blocks 11 and

The 12 pulses are fed to the first and second inputs of the imaging unit 5 output pulses. In this block the conversion is carried out

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positive impulses from the output of the second impulse recovery unit in impulsive polarity and their filling with positive impulses from the output of the first repair impulse block. On the shape of the output shaper 5, a quasitroic phase is formed) which is removed from, which is the output signal of the phase dependence. Code and 15 are combined in OR 14, since the code combination or overlap

of the outputs of blocks 13. The principle of operation lies in that between a short pulse and a clock is high (TI) from the generator (Fig. 2k). What is more the more pa of signals, the more the VI fits in the Internet and the information in the parallel is fed to kos 13 and 15, This information controlling for ne determines its coefficient It is fed from the block of elements IL decoder 16, the decoder 21 on n of block 24 Comparison of input 24 is continuous with respect to the position of trigger 23 on the basis of its counter code and high-frequency im- pulses of 25 pulses (on the codes of the blocks of block 24 compare, a pulse arises, which first counts the counting trigger time of its tilting, thus the signals of the regenerator.

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cash device (FIG, 2h),

Short pulses from the outputs of the first 8 and second 9 pulse detection units, as well as from the second g outputs of the first 11 and second 12 pulse recovery units, are fed to the four inputs of the control unit 10, When the regenerator enters synchronization at the beginning of operation or as a result of a long interruption (alarm ) at the first output of control unit 10, pulses appear from the outputs of the first 8 and second 9 pulse detection units. In the steady state mode of operation of the regenerator, at the first control unit 10, there are pulses with moves of the first 11 and second 12 pulse recovery blocks. The signal at the second output of the control unit 10 determines the mode of operation of the pulse recovery units when entering synchronization and in steady state.

Short pulses from the first output of the control unit 10 (Fig. 2i) are fed to the second input of the signal advance detection unit 13 and the second input of the signal delay detection unit 15. The third and fourth inputs of these blocks receive clock signals from the first (inverse) and second (direct) outputs of the counting trigger 20 (Fig. 2m, n). High-frequency pulses of the pulse generator 25 are fed to the first inputs of blocks 13 and 15 (Fig. 2k ),

In blocks 13 and 15, the detection or delay of the phase of information pulses from the first output of control unit 10 (Fig. 2i) with respect to the clock phase from the first and second outputs of the counting trigger 20 (Fig. 2m, n) occurs.

When detecting a phase difference 55 between the information and clock signals at the code outputs of blocks 13 and 15, a signal appears in the parallel code, the values of which change

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 phases) are removed from

20

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50 .

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depending on the magnitude of the phase difference. The code outputs of blocks 13 and 15 are combined in the block of elements OR 14, since the same code combinations in terms of the absolute lag or phase advance correspond to the same absolute value. Phase advance or lag signals (sign

additional

the outputs of blocks 13 and 15 (Fig. 2o). The principle of operation of blocks 13 and 15 is that the time interval between the short information pulse and the clock pulse is filled with high-frequency pulses from the pulse generator 25 (Fig. 2k). The longer this interval, i.e. the larger the phase difference of these signals, the greater the number of HIs in the interval. Then V is read and the information about their number in the parallel code on the buses is fed to the code output of blocks 13 and 15. This information is the control for the first counter 23, determining its division factor. It is fed from the code output of the block of elements OR 14 through the first decoder 16, the accumulator 18, the second decoder 21 to the first code input of the comparison block 24. Information about the position of the triggers of the first counter 23 is transmitted to the second code input 24 at the input of its code output. High-frequency pulses from the pulse generator 25 (Fig. 2k) are continuously fed to the input of this counter. its output gives rise to a pulse (Fig. 2L), which zeros the first counter 23, controls the counting trigger 20, once again tilting it and thus generating the regenerator clock frequency signal.

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To ensure the inertia of tracking the phase of information pulses, use the decoder 16, the I18 drive, the decoder 21, and the second I counter 17. This inertia is equivalent to a certain figure of figure of merit of the clock separator circuit in known regenerator circuits. The inertia (quality factor) may automatically change (increase or decrease) depending on the disturbance stop on the communication line. As a result, decreases

the probability of incorrect registration of information pulses, since the phase of the clock sync pulses in the proposed device, in any case, has time to adjust to an abrupt change in the phase of information pulses.

If the phase of the information pulse exactly coincides with the phase of the clock pulse on the buses of the code outputs of blocks 13 and 15, they will be zero. With increasing phase difference of these pulses in the direction of advance or delay on buses, the code outputs of blocks 13 and 15 appear a binary signal (in parallel code), which can vary from 000000 to 100000, which corresponds to the decimal numbers 0-32. This is the number of high-frequency pulses that were laid in the time interval between the information and clock pulses during the phase shift between these two signals.

The code outputs of blocks 13 and 15 through the block of elements OR 19 are connected to the code input of the first decoder 16. The signal on the buses of the code output of the decoder 16 is 0000 and is stored when the binary signal at the output of blocks 13 and 15 changes from 000000 to 000011, i.e. from O to 3.

The combination of 0000 will also be on the tires of the code output of the accumulator 18.

If the phase shift between the information

and a clock pulse is equal to 4 high-frequency pulses, then the output of blocks 13 and 15 is the binary signal 000100 and the output of the decoder 16 is 1000 signal. This combination 1000 is fed to the code input of the accumulator 18. In this case, combinations do not cause a change in the state of the accumulator, and one is remembered. When a short pulse arrives at the control input of accumulator 18 from an additional output of blocks 13 and 15 or through an OR element 19, the combination 1000 is at the accumulator code output and is held there until the next control pulse arrives.

the change of the binary signal at the code output 13 or 15 from 000100 to 000111, i.e. from 4 to 7. high-frequency pulse filling phase shift, does not cause a change in number

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1000 binaries on the code output of the drive 18.

A consecutive increase in the binary combination at the output of the BOOP or OSU from 000000 to 001000 inclusively causes the sequential appearance of two units on the code output of the decoder 16 at the moments when the code input contains the combinations 000100 and 001000. These two units are fixed in accumulator 18 and c the arrival of a short pulse at its control input at the output of accumulator 18 will be a combination of 1100. If the phase shift between the information and clock pulses in blocks 13 and 15 is greater than 8 high-frequency filling pulses, then the binary signal code outputs of these blocks continues to grow. At the moment when the filling pulses are 16 (010000), a combination 1110 is formed at the output of the storage ring 18, and if these filling pulses are 32 (100000), then there will be a combination 1111.

Thus, a stepwise determination of the magnitude of the phase shift between information and clock pulses occurs. The values of these phase shifts are equal to 0.4,8,16,32 high-frequency filling pulses, i.e. About 8, 16, 32, 64% of the duration of a single pulse. The zero phase shift corresponds to the code combination at the output of the drive 0000; 8%, phase shift corresponds to 1000; 16% to phase shift corresponds to 1100J; 32% to phase shift corresponds to 1110, 64% to phase shift corresponds to 1111.

The signal from the code output of the accumulator is fed to the one input of the second decoder 21, where the formation of a code combination occurs, under the action of which the phase shift between information and clock pulses is reduced, I

In order to form the phase symbol (advance or lag) when forming the code combination in the second decoder 21, I send the full and inverse signals from the RS flip-flop 22 outputs to the first and second additional inputs of the decoder 21. trigger 22 pulses are used from additional outputs 13 and 15.

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Consider the case when there is no phase difference between the information and clock pulses or it is less than 4 filling pulses. Then the code input of the second decoder 21 will be a combination 0000, and at its first and second additional input signals 01 or 10. In this case, the output 110010 (50 in the decimal system) is formed at the output 2 of the decoder.

If the phase difference between the information and clock pulses is from 4 to 7 high-frequency filling pulses, then a combination of 1000 appears at the code input of the decoder 21, and a signal 10 is detected at its first and second additional inputs when detected at phase 13 or 01 at phase 15 detected in block 15. In the first case, a combination of 110001 (49) appears at the code output of the decoder 21, and in the second case, 110011 (51).

With 4 phase variations between information and clock pulses ranging from 8 to 15 high-frequency filling pulses, a combination of 110,000 (48) or 110100 (52) occurs at the code output of the decoder 21, which are determined by the signal on

additional inputs of the decoder 21. I

Phase divergence from

16 to 31 filling pulses cause the appearance on the code output of the decoder 21 of the combination 101110 (46) or 110110 (54), depending on the advance or lag of the information signal phase.

Leading or lagging the phase by an amount equal to or equal to or more than 32 filling pulses, causes the code output of the decoder 21 of the 101010 (42) or 111010 (58) combination, respectively.

The signal from the code output of the second decoder 21 is fed to the first code input of the comparator unit 24. A signal from the code output of the first counter 23 is supplied to the second code input of the comparator unit 24.

The code combination, for example 101110 (46), on the first code input of the comparison unit 24 does not change during one or several clock intervals (the signals forming it are fixed in the accumulator

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18 and RS flip-flop 22. The combinations on the buses of the second code input of the comparator block 24 vary continuously according to the position of the flip-flops included in the first counter 23. When the counter 23 counts a certain number of pulses, for example 46, the state of its triggers for this case 101110. As soon as the combinations on the first and second code inputs of the comparison unit 24 coincide, a signal appears at its output (Fig. 2L), which zeroes the first

15 counter 23. Next, counter 23 counts again, for example, 46 Pulses and zeroes under the action of a signal from the output of comparator unit 24, etc. If the combination at the first input of a 2Q kA 24 comparison, for example, 110110, then a coincidence signal at the output of the comparison unit 24 appears every 54 high-frequency pulses.

Short pulses from the output of the block.

25–24 comparisons arrive at the input of counting trigger 20 and control its operation. This trigger generates clock pulses, the frequency of which may vary depending on the frequency

2Q signal from the output of block 24 comparison.

In the absence of a phase shift between the information and clock pulses, a signal at the output of comparator 24 appears every

50 high-frequency pulses, and

Whose

The accuracy of clock pulses at the output of counting trigger 20 is exactly equal to the duration of undistorted information pulses. one,

40 When the information pulse clock appears, for example, by the amount of 8 high-frequency filling pulses, a short signal appears at the output of the comparison unit 24 after every 48 high-frequency pulses. The consequence of this is an increase in the frequency of the clock sequence at the output of the counting trigger 20. After not many clock intervals, the phase shift between the information and clock pulses is compensated, which is detected in block 13 and block 15, which enters the signal through de 55 encoder 16, accumulator 18, decoder 21 in block 24 comparison. As a result, the clock frequency at the output of the counting trigger is reduced to a normal value.

In order to avoid overcompensation of the phase shift during a long pause between information pulses, a second counter 17 is inserted into the device. At its information input, pulses are output from the output of the comparison unit 24, and the control input is pulses from the output of the OR 19 element. The second counter 17 appears after every sixth pulse of the comparator block 24. By the same signal, the counter through the element OR 19 is reset to zero. In addition, the counter is reset to zero from pulses from additional outputs. blocks 13 and 15, which zero it regardless of how many pulses he managed to calculate.

Suppose that between the information and clock pulses there was a phase shift of 4 high-frequency pulses. The code combination, proportional to this phase shift, was fixed at the first input of comparator block 24. After this, the next information pulse did not arrive at the input of the regenerator for 10 clock intervals.

Under the action of the signal at the first code input of block 24, the comparison of the clock frequency at the output of the counting trigger changed in such a way that the phase shift with each beat decreased more and more. After the fourth since the detection of the phase difference of the pulse from the output of the unit 24, the comparison of the phase of the last information pulse and the clock pulse is the same.

If there were no second counter 17, then for the remaining 6 clock intervals before the appearance of the information pulse, a phase would be compensated for 6 high-frequency filling pulses or 12% of the duration of a single clock interval. Using the counter 17 allows you to prevent such phase compensation in the long pauses between information by pulses. After the 6th pulse from the output of the comparator unit 24, a signal appears on the code of the second counter, which passes through the element OR 19 and, falling on the control input of the accumulator 18, resets the code combination fixed in it. Since the input is accumulated

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body 18 at this time is a combination; 0000, then it will be at its output.

Under the action of this combination, the signal output of the second decoder 21 generates a signal 110010, and at the output of the counting trigger 20. the contact pulses have a frequency that exactly coincides 1Q with the clock frequency of the information signal. Thus, further correction of the phase of the clock pulses of the regenerator is terminated before the arrival of the next information pulse. Block 8 (Fig. 3) includes the unit detector using the integration method, consisting of the first element AND 26, the first counter 27, the first decoder 28, the first element OR 29, the third element OR 30, the RS flip-flop 31 and the third element AND 32 , also a gating unit detector, consisting of the fourth element AND 33, 25 pulse generator 34 and delay element 35, a zero detector, consisting of inverter 36, second element 37, second counter 38, second decoder 39, second element OR 40

Block 8 works as follows.

The information pulses from the output of the pulse former 6 (Fig. 1) arrive at the first input of the element 26, to the first input of the element 33 and to the input of the inverter 36. To the second inputs of the elements 26 and 37, high-frequency filling pulses are output from the output of the pulse generator 25, (Fig. 1).

When an information pulse appears at the first input of element I 26, high-frequency filling pulses appear at the output, the number of which is proportional to the duration of the input pulse. If the information pulse is undistorted, then the number of high-frequency filling pulses will be 50.

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50 The filling pulses are counted in the first counter 27 and at its code output a signal arriving at the code input of the first decoder 28 appears. As soon as the counter

If 5527 counted 25 fill pulses (50% of the duration of the undistorted information pulse), then a signal appears at the output of the first decoder 28. This signal resets to zero state, the counter 27 and the counter 38 through the elements OR 29 and OR 40 and, passing through the element OR 30, causes the RS flip-flop 31 to trigger, at the input of which a unit potential appears. This potential is applied to the first input of the element AND 32.

The information pulse is thus detected, but at the output of AND 32 (the output of the pulse detection unit) it appears only after detecting zero. This is done so that the unit detector using the integration method does not react to the fragmentation of information pulses.

Zero detection is as follows.

The information signal after passing through the inverter 36 is fed to the first input of the element I 37-, the second input of which receives high-frequency filling pulses. If the input 1 and the inverter 36 signal 1, then the filling pulses do not pass to the output of the element 37, If the input of the inverter is 36 o, then the filling pulses arrive at the input of the second counter 38. These pulses are counted in this counter 38 and on its code the output of a signal arriving at the code input of the second decoder 39. As soon as the counter 38 counts 25 filling pulses, a signal appears at the output of the second decoder 39. This signal is reset to the zero state by the counter 27 through the element OR 40, in addition, this signal is fed to the second input of the AND 32 element. At the moment this signal arrives at the output of the AND 32 element, a unit detection pulse appears, which is fed further to the input of the block recovery pulse 11 (Fig. 1). In addition, the pulse 27 and the RS flip-flop 31 are reset to the zero position by a pulse from the output of the element 32.

If the input information signal has a duration of less than 50% of the undistorted and cannot be detected by the integration method, it can be detected by the gating method. For this, the input information signal is applied to the first input of the AND element 33, to the second input of which short clock pulses are applied.

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getting right in the middle of information. Clock pulses come from the output of the counting trigger 20 (Fig. 1) through the delay element and. shaper short pulses to the second input element And 33.

When an information pulse is detected at the output of element 33, a signal appears that passes through the element OR 30 and overturns the RS flip-flop 31. Thus, the probability of detecting a single information pulse increases significantly.

The pulse recovery unit 11 consists of the AND unit 41 of the switch 42, the first RS flip-flop 43, the second RS flip-flop 44, the first pulse shaper 45, the second pulse shaper 46, the third pulse shaper 47 and the delay element 48 (Fig. 4).

The pulse recovery unit 11 5 operates as follows.

At the first input of the AND circuit, short information pulses are received, which are detected in block 8. The second input of the And 41 element is supplied with clock pulses from the output of the counting trigger 20 (Fig. 1). By using the delay element 48, the clock pulses are delayed by such a value that the short information pulses fall exactly on their middle. This is done in order to prevent the passage of interference with a duration of more than half of the information pulse, as a result of which it was detected in block 8 as an information

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signal, on the first RS-trigger 43. Speech

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an adat on interference, which appeared in the interval, where only the zeros of the information signal should be in normal conditions.

The signal from the output of the element And 41 is fed to the first input of the switch 42 and then from its output to the input of the first RS flip-flop 43. At the second

the input of the switch 42 is supplied with a signal from the output of block 8 (Fig. 1). The switch 42 is controlled by a signal from the control unit 10. In the acquisition mode from

control unit 10 (Fig. 1), a signal 1 is received at the control input of the switch 42, under the action of which the output of the switch 42 is connected to its second input. In that

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In this case, information pulses, element I 41, are fed to the input of the first RS flip-flop 43.

Thus, it is possible to reduce the number of erroneous pulses during the time when the regenerator enters synchronization.

After entering the regenerator in

the first and second inputs of the control unit (Fig. 1), where they are fed to the first and second inputs of the g element OR 49 (Fig. 5). In addition, information signals taken from the second outputs of block 11 are fed to the third and fourth inputs of control block 10, from where they come to

synchronism at the control input of the first and second inputs of the OR 19 tator element comes signal O from the control unit 10, under the action of which the output of the switch 42 is connected to its first input.

As a result, the information pulses enter the input of the RS flip-flop 43 only after they pass through the AND 41 element.:

Under the action of an information pulse from the output of the switch 42, the RS flip-flop 43 tilts and an O signal appears at its inverse output. In this state, the RS flip-flop 43 is held until the arrival of the counting flip-flop 20 (Fig. 1). This clock pulse is shortened in the second pulse shaper 46 and, arriving at the R input of the RS flip-flop 43, returns it to its original state. At the same time, the signal 1 is generated at the inverse output of the RS-trgr 43. This pulse passes the first pulse shaper 45, where it is shortened in duration and fed to the S input of the second RS flip-flop 44, This circuit also triggers at its output A single potential is maintained until a signal arrives at the R input. This signal is the clock frequency pulses coming from the inverse output of the counting trigger 20 (Fig. 1). The pulses are shortened in the third pulse shaper 47 and are fed to the input of the second RS flip-flop 44,

Thus, at the output of the second RS flip-flop 44 (output of block 11), reconstructed information pulses are formed, the duration of which is equal to the duration of the clock pulses of the registrar.

The control unit 10 (FIG. 5) consists of the first element OR 49, the second element OR 50, the counter 51, the RS flip-flop 52, the element 53 of the delay, and the one of the switch 54.

Information pulses from the outputs of the first 8 and second 9 pulse detection units are fed to

(Fig. 5). In the mode of stable functioning of the regenerator, information pulses arrive simultaneously at the elements OR 49 and 50. The counter

15 51 is triggered by the first impulse from the output of the element OR 49, but after a short period of time, determined by the element of delay 53, -. va is reset to oh pulse with

20 output element OR 50. The signal at the output of the counter 51 can occur only if 2 pulses arrived at its input, which were not pulsed from the output

25 delay elements 53. Thus, the signal at the output of counter 51 appears only if there are pulses at the input of the element OR 49 and are absent at the input of the element OR 50. This

30 occurs when there is a large discrepancy between the phases of the information pulse relative to the clock in the mode of the regenerator entering synchronization. In this case, a single pulse from the output of the counter 51 tilts the RS-flip-flop 52, which is held in this state until the pulse arrives at the input of the OR 50 element. the output of the RS flip-flop 52 is used as a control for the switch 54 of this control block 10, and also for the switch 42 in block 11 (FIG. 4).

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If signal 1 appears at the control input of switch 54, its output is connected to its first input connected to the output of the element OR 49. Thus, information pulses coming from the output 50 of switch 54 (the output of control unit 10 ) to the first inputs of blocks 13 and 15, are removed in this case from the outputs of blocks 8 and 9 (Fig. 1).

When a synchronizer of the regenerator 55 appears relative to a linear signal at the output of the element OR 50 (Fig. 5), information pulses appear, which reset counter 0 51 and RS flip-flop 52 into O.

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the first and second inputs of the control unit (Fig. 1), where they are fed to the first and second inputs of the element OR 49 (Fig. 5). In addition, information signals taken from the second outputs of block 11 are fed to the third and fourth inputs of control block 10, from where they come to

the first and second inputs of the element OR 1

the first and second inputs of the element OR 19

(Fig. 5). In the mode of stable functioning of the regenerator, information pulses arrive simultaneously at the elements OR 49 and 50. The counter

51 is triggered by the first impulse from the output of the element OR 49, but after a short period of time, determined by the element of delay 53, -. va is reset to oh pulse with

the output of the element OR 50. The signal at the output of the counter 51 can occur only if 2 pulses have arrived at its input, which have not been reset by pulses from the output

delay element 53. Thus, the signal at the output of counter 51 appears only if there are pulses at the input of the element OR 49 and they are not present at the input of the element OR 50. This

occurs when there is a large discrepancy between the phases of the information pulse relative to the clock in the mode of the regenerator entering synchronization. In this case, a single pulse from the output of the counter 51 tilts the RS-flip-flop 52, which is held in this state until the pulse arrives at the input of the OR 50 element. Signal c. the output of the RS flip-flop 52 is used as a control for the switch 54 of this control block 10, and also for the switch 42 in block 11 (FIG. 4).

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If signal 1 appears at the control input of switch 54, its output is connected to its first input connected to the output of the OR element 49. Thus, information pulses from the output of switch 54 (control unit 10 output) to The first inputs of blocks 13 and 15, in this case, are removed from the outputs of blocks 8 and 9 (Fig. 1).

When synchronization of the regenerator occurs relative to a linear signal at the output of the element OR 50 (Fig. 5), information pulses appear, which reset counter 0 51 and RS flip-flop 52 into O.

during the RS flip-flop 52, a signal O is generated, under the action of which the output of the switch 54 is connected to its second input, which is connected to the output of the element OR 50. Thus, the pulses coming from the output of the control block 10 to the first inputs of blocks 13 and 15 are removed in In this case, from the second blocks 11 and 12, the use of the control block 10 makes it possible to increase the noise immunity of synchronization and to increase the speed of entry into synchronism without interrupting the transmission of information signals.

The signal advance detection unit 13 (Fig. 6) consists of the first element And 55, the second element And 56, the RS flip-flop 57, the first

15 If a short information pulse at the first input of the And 55 element lags behind the clock pulse (forward), then the And 56 element remains closed and at its input the signal does not

delay element 58, the second element arises, in this case

This 59 delay, the first imager 60 pulses, the second imager 61 pulses and the counter 62.

Information pulses from the first output of the control unit 10 are fed to the first input of the block 13 (Fig. 1), which, inside the block is connected to the first input of an And 55 element. To the second input of the And 55 element, clock pulses come from the second (direct) output of the counting trigger 20 (Fig. 1).

If a short information pulse is ahead of the clock pulse (forward), i.e. If a single pulse at the first and second input of an And 55 element coincides, a pulse also appears at its output. Under the action of this pulse, an RS-flip-flop 57 is triggered, the direct output of which is connected to the first input of the element I 56. The signal from the RS flip-down -57 element I 56 opens and the high-frequency filling pulses from the pulse generator 25 pass to the counter input. At the code output of counter 62 (output of block 13) code combinations appear that are proportional to the number of filling pulses that go to the input of counter 62, i.e. phase shift between information and clock pulses.

The supply of high-frequency filling pulses is stopped with the arrival at the R input of the RS flip-flop 57 of the leading edge of the clock pulse (inverse), under the action of which O appears at the forward output of the RS flip-flop 57, and at the inverse 1. Signal

to the operation of the signal delay detection unit.

FIG. 7 shows a diagram of the implementation of the delay detection unit 25 of the HOSE signal (15), the block consists of the first element AND 63, the second element AND 64 of the RS flip-flop 65, the delay element 66, the first driver 67 of the pulses, the second one

30 bodies 68 pulses, counter 69 and

key elements 70, I

Information signal from the first

the output of the control unit 10 (FIG. 1) is fed to the first input of the first

35 of the element AND 63, to the second input of which clock pulses are supplied from the first (inverse) output of the counting trigger 20 (FIG. 1). These clock pulses are also fed to the first

40 is the input of the second element AND 64, to the second input of which high-frequency filling pulses arrive, and to the third input - a signal from the inverse output of the RS flip-flop 65,

45 If the clock pulse (inverse) arriving at the first inputs of the And 63 and 64 elements has single values (the delay detection zone), then the And 64 elements at the output

50 are filling pulses. These pulses are counted by counter 69, and code combinations appear on its code output. However, the signal from the code output of the counter 69 is not at 55 output of block 15, since the key elements to which it was applied at a given time interval are blocked by the potential O from the direct output of the RS flip-flop 65,

from the inverse output of the RS flip-flop 57, the passage through the first delay element 58 and the first shaper 60 pulses, comes from the auxiliary output of the block 13 of the SHSh 19 element and the RS-triger 22 (Fig. 1). By the same clock front (inverse), after a small interval i,

defined by the first delay element, the counter is reset to 0, the reset is made with a short pulse from the output of the second driver.

If a short information pulse at the first input of the And 55 element lags behind the drop of the clock pulse (direct), then the And 56 element remains closed and at its input the signal does not

to the operation of the signal delay detection unit.

FIG. 7 shows a diagram of the implementation of the delay detection unit5 of the HSU signal (15). The block consists of the first element AND 63, the second element AND 64 of the RS flip-flop 65, the delay element 66, the first driver 67 of the pulses, the second one

0 bodies 68 pulses, counter 69 and

key elements 70, I

Information signal from the first

the output of the control unit 10 (FIG. 1) is fed to the first input of the first

5 of the AND 63 element, to the second input of which clock pulses are supplied from the first (inverse) output of the counting trigger 20 (FIG. 1). These clock pulses are also fed to the first

0 is the input of the second element AND 64, the second input of which receives high-frequency filling pulses, and the third input receives the signal from the inverse output of the RS flip-flop 65,

5 If the clock pulse (inverse) arriving at the first inputs of the AND 63 and 64 elements has single values (the delay detection zone), then the AND 64 elements at the output

0 are fill pulses. These pulses are counted by counter 69, and code combinations appear on its code output. However, the signal from the code output of counter 69 is not equal to 5 at the output of block 15, since the key elements to which it was applied at a given time interval are blocked by potential O from the direct output of RS flip-flop 65,

When a data pulse is out of phase at the first input of the element 64, a pulse appears at its output, which causes the RS flip-flop 65 to work. On the inverse output of the RS flip-flop 65, an O occurs, which closes the AND 64, stopping the arrival of pulses filling to the input of the counter 69. At the same time, the pulse 1 from the direct output of the RS flip-flop 65 opens the key elements 70 and the code combination, proportional to the phase shift between the information and the clock pulse, appears at the output of the block 15. The signal from the forward signal stroke RS-trigger 65 extending through the element 66 and the first delay pulse generator 67 is supplied with an additional output block 15 for IL-1 and 19 elements RS flip-flop 22 (FIG. 1). The entire circuit is reset to its initial state by the leading edge of a clock pulse (direct) which is fed to the R input of the RS flip-flop 65, and through the second pulse shaper 68 to the control input of the counter.

Comparison unit 24 (FIG. 8) consists of two-input elements AND 71-81 of two-input elements OR 82-86, a six-input element I.87 and inverters 88-92. At the bottom of FIG. 8 shows the buses of the first code input of the comparator unit 24 connected to the code output of the second decoder 21 (FIG. 1). In the upper part of FIG. 8, the buses of the second code input of the comparator unit 24 are shown, connected to the code output of the first counter 23 (FIG. 1). The first digit of the first counter (1658,4,2,1) contains a direct and inverse output with the exception of the high bit (32), which has only a direct output.

Inverse signals in bits (16.8, 4, 2) from the core, the output of the second depfractor (at the first code input of the reference unit) are formed using inverters 88–9. The high order signal (32) of the inversion not exposed.

Block 24 is active; it works in the following 15Im fashion.

Before the half slot: - ,, a signal with the code combination 110010 (50) acts on the first code input of the comparison block for some time.

In this case, the single symbols of this combination go to the second inputs And 71, 72, 78, and zero to the second inputs of the elements And 74, 76, 80. Signals 1 are received at the second inputs of the And elements 75, 77, 81, received after inversion of zeros in bit d 8,4,1. The first inputs of the two-input elements And 70-80 receive continuously varying signals from the second code input of this block (from the code output of the first counter 23). How ToxibKo code combination on the second

When the code input of the comparator unit is equal to 110010, then signals 1 appear at the outputs of the AND 71, 72, 75, 77, 78, 81 elements, OR - during which a pulse appears that is an output for the comparison unit 24. Similarly, the unit operates when the signal changes at the first

code input of the comparison block.

The use of this proposal makes it possible to create a digital signal regenerator adapting to different states of the disturbance situation on the communication line. To increase

The interference level in the pereaepfaTop line responds by reducing the inertia of their synchronization circuits. As a result, the correlation between the information pulses arriving at the input of the regenerator and the clock sync pulses generated inside the regenerator increases. The result is a reduction in the probability of errors when the digital signal is restored in the regenerator.

In the proposed device, an information detection circuit is applied.

pulses based on the simultaneous use of the gating and integration method. The integration is performed by filling the information signal with high frequency pulses and their subsequent counting. The integration scheme is not associated with the regenerator clock pulses and therefore allows, with greater certainty,

detect informational sprinkles. The simultaneous use of two methods of detecting information pulses allows one to successfully reconstruct signals that are subject to

191

marginal distortion m and crushing m This contributes to an even greater increase in the fidelity of the transmitted information.

Claims (1)

Invention Formula Adaptive regenerator containing output pulse shaper: adjustable artificial line, the output of which is connected to the inputs of the separation unit through a correction amplifier, the third output of which through the automatic gain control unit is connected to the control input of the adjustable artificial line, whose information input is the input of the adaptive regenerator, which is distinguished by the fact that, in order to ensure noise immunity, : the pulse generator, the control unit, the first counter, the signal advance detection unit, the RS trigger, the counting trigger, the second counter connected in series, and the OR element whose output is connected to the control input of the second counter, are entered; signal lag the OR element block, to the second code input of which the first output of the signal advance detection unit is connected, the first decoder, the accumulator, to the control input of which the output of the OR element, the second decoder, is connected, the RS-flip-flop switches are connected to the second and third inputs, and a comparison unit, the output of which is connected to the information inputs of the counting trigger of the first and second counters, while the first output of the separation unit is connected through the inputted successively 6349020 the first pulse generator, and the first pulse recovery unit to the first input of the output pulse bodies, to the second input of which the second output of the separation unit is connected through the second pulse generator connected in series, the second 10 a pulse detection unit and a second pulse recovery unit, and the output of the pulse generator is connected to the information input of the first counter, the output of which is connected -15 to the second code input of the comparison unit, to the first inputs of the signal advance detection unit and the signal delay detection unit, to the first clock inputs the first and second pulse detection units, the outputs of which are connected to the first and second inputs of the control unit, to the third and fourth inputs of which the second are connected 25 outputs of the first and second pulse recovery units; the first output of the control unit is connected to the second inputs of the signal detection detection unit, the output of which is connected to 30 to the second input of the OR element and the first code input of the RS flip-flop, and the signal delay detection unit whose output is connected to the third input of the OR element and the second code input of the RS flip-flop, the second output of the control unit to the control inputs of the first and second pulse recovery units , to the first and second synchronization inputs of which, to the third and fourth inputs of the signal advance detection unit and the signal delay detection unit, the first and second counts of the counter trigger 45 are connected respectively Phi2 .:} Fiu.5 JLon.Bbtf. Code FIG. 6 Lop was Nod.v to / x. From ntpfoto cvfrnuuxa Hl "in From Smopoto dtwutppofnopu IHute Editor T. Lazorenko Compiled by L.Timoshina Tehred M. Khodanich Proofreader V. But ha Order 6382/55 Circulation 636 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4