RU1809543C - Cycle synchronizing device - Google Patents

Abstract

The invention relates to radio engineering and can be used in discrete message transmission systems and in systems with digital methods for modulating analog signals. The purpose of the invention is to reduce the time to restore synchronism after signal loss. The cycle synchronization device comprises a sync group identifier 1, a first error analyzer 2, a frequency divider 3, a decisive node 4, a first divider — a distributor 5, a second error analyzer 6, a lack of synchronism detector 7, a phasing signal generator 8, a trigger 9, a counter 10 , the second divider-distributor 11, the invention relates to radio engineering and can be used in receivers of discrete message transmission systems and systems with digital methods for modulating analog signals. The aim of the invention is to reduce the time to restore synchronism after signal loss. The drawing shows a structural diagram of a device for synchronizing cycles, the device for synchronizing cycles contains a sync group identifier 1, a first error analyzer 2, a divider 3 additional counter 12, an amplitude detector 13, a threshold block 14, an inverter 15, an AND-NOT element 16 and an OR element 17 To reduce the time of restoration of synchronism after signal failures, an additional counter 12, an amplitude detector 13 and threshold block 14 were introduced (Fig. 2), as a result of which the output voltage at the time of the signal loss in the communication channel mplitudnogo detector 13 decreases, the output of the threshold unit 14 is formed by a logic zero signal, and an additional counter 12 is started to count. In this case, the final establishment of a new synchronism in the second splitter-distributor 11 occurs at the moment f the counting of the additional counter 12 is finished. The time to restore synchronism after the signal disappears is determined by the counting coefficient of the additional counter 12. The range of synchronization recovery time after short-term signal failures is insignificant compared with cycle time. 1 ill. frequency, the deciding node 4, the first divider-distributor 5, the second analyzer 6 errors, the detector 7 lack of synchronism, the shaper 8 of the phasing signals, trigger 9, counter 10, the second divider-distributor 11 additional counter 12, amplitude detector 13. threshold block 14, an inverter 15, an I-NB element 16. and an OR element 17. The information input of the device is the input of the sync group identifier 1. The clock input of the device is connected to the clock inputs of a frequency divider 3 frequencies;

Description

the second and second divider-distributors 5, 11, counter 10 and additional counter 12. An additional input of the device is the input of the amplitude detector 13. The output of the sync group identifier 1 is connected to the first inputs of the first and second error analyzers 2, 6. The first and second outputs of the first error analyzer 2 are connected, respectively, to the first and second inputs of the frequency divider 3, and also, respectively, to the first and second inputs of the decision node 4. The first output of the decision node 4 is connected to the control input of the frequency divider 3. The second output of the decision node 4 is connected to the first input of the phasing signal generator 8. The output of the frequency divider 3 is connected to the second input of the first error analyzer 2 and to the second input of the phasing signal generator 8. The first and second outputs of the second analyzer 6 errors are connected, respectively, with the first and second inputs of the detector 7 lack of synchronism. The output of the detector 7 lack of synchronism is connected to the installation input of the trigger 9 and the first input of the AND-NOT 16. The output of the AND-NOT 16 is connected to the control input of the counter 10. The output of the counter 10 is connected to the first input of the OR 17. The output of trigger 9 is connected to the third input of the phasing signal generator 8. The first output of the phasing signal generator 8 is connected to the reset inputs of the detector 7 for lack of synchronism and trigger 9. The second output of the phasing signal generator 8 is connected to the installation input of the first splitter-distributor 5. The first output of the first splitter-distributor 5 is connected to the second input of the second error analyzer 6 and with the fourth input of the phasing signal generator 8. The remaining outputs of the first splitter-distributor 5 are connected to the corresponding installation inputs of the second splitter-distributor 11. The output of the amplitude detector 13 is connected to the input of the threshold device 14. The output of the threshold device 14 is connected to the control input of the additional counter 12. The output of the additional counter 12 is connected to the input of the inverter 15 and with the second input of the OR element 17. The output of the inverter 15 is connected to the second input of the AND-NOT element 16. The output of the OR element 17 is connected to the control input of the second divider bodies 11. Yield -raspredelitel second divider 11 is the output device.

The device synchronization cycles works as follows. We believe that

in order to provide synchronization between the cycles of the receiver in the transmitter in each cycle of N cycles, a fixed-time concentrated sync group is formed at the same cycle positions. At the information input of the device, a serial digital information code is entered by the Sync groups entered into it from the output of the demodulator. At the output of the sync group identifier 1, response signals are generated for both the sync group and the code groups of the information signal similar to the sync group. These response signals are fed to the first inputs of the first and second error analyzers 2, 6, to the second inputs of which test signals from the outputs, respectively, of the frequency divider 3 and the first splitter divider 5 are supplied. Each of the error analyzers 2, 6 generates at its first output, a signal of correct reception in the case when the test signal coincides in time with the response of the sync group identities 1. If at the moment of arrival of the test signal, the response signal of the sync group identifier 1 is absent, then at this moment an error signal is generated at the second output of the corresponding analyzer 2 or 6 of errors.

The first error analyzer 2, frequency divider 3, and decision node 4 serve to quickly detect a lack of synchronization, to search for and fix a new synchronism state. When some small number of error signals come from the output of the first error analyzer 2, the decision node 4 goes into search mode

synchronism and generates at its first output a control signal allowing the frequency divider 3 to be controlled by signals from the output of the first error analyzer 2. In this case, the divider stops

3 frequencies are carried out according to the first error signal, and start - according to the first signal of the correct reception of the sync group. After the frequency divider 3 finds a new synchronism state and some small number of signals of the correct reception of the synchronization group arrive, the decision node 4 switches to the synchronization state fixation mode and generates a control signal at its first output.

providing non-stop operation of the frequency divider 3, and also, at its second output, a signal preparing the phasing signal shaper 8 for comparing the phases of the frequency divider 3 and the light splitter-distributor 5.

The inputs of the detector 7 with no synchronism receive a signal of correct reception and an error signal from the outputs of the second analyzer 6 errors. At the output of the detector 7 with no synchronism, a signal of the lack of synchronism of positive polarity is generated when another M error signals arrive at its input. The lack of synchronism signal sets the trigger 9 to a position allowing the comparison of the phases of the frequency divider 3 and the first divider-distributor 5 in the phasing signal generator 8. In addition, in the case when a logical unit signal is present at the output of the inverter 15, a positive signal of a lack of synchronism at the first input of the IN-H E 16 element leads to the formation of a logic zero signal at its output, which starts counter 10.

When the trigger 9 is installed and if there is a signal at the second output of the decision node 4 that prepares the shaper 8, the phasing signals, the shaper 8 of the phasing signals compares the phases of the frequency divider 3 and the first splitter-distributor 5, generating a signal at this moment at its first output, resetting, trigger 9 and detector 7 lack of synchronism. In addition, in the event of a phase difference between the frequency divider 3 and the first splitter 5, the phasing driver 8 generates a signal at its second output, which sets the phase of the first splitter 5 in accordance with the phase of the frequency divider 3.

After starting the counter 10 with a negative polarity signal from the output of the NAND 16 element, the counter 10 starts counting the clock pulses and generates a logic unit signal at its output. After K clock intervals have elapsed, counter 10 stops counting and generates a logic zero signal at its output, remaining in this state until the next triggering signal arrives.

An additional input of the device receives a signal directly from the output of the communication channel. The amplitude detector 13 generates at its output a high voltage signal when a signal at the output of the communication channel is present, and a low voltage signal when the signal disappears in the communication channel. The threshold device 14 compares the voltage at its input with a threshold level equal to about half the sum of the maximum and minimum values of the input voltage.

When the input voltage exceeds the threshold level, the output of the threshold device 14 generates a signal of a logical unit, otherwise, a signal 5 of a logical zero. Therefore, when a signal in the communication channel is present, the output signal of the threshold device 14 is a logical unit, and at the time of the loss of a signal, a logical zero. When the additional input 12 of the logic zero signal arrives at the direct input, it starts counting clock pulses and generates a logic unit signal at its output at this time. After the L clock intervals 5, an additional counter 12 stops counting and generates a logic zero signal at its output, remaining in this state until the next one arrives. starting trigger signal. When a logic unit signal is present at the output of the additional counter 12, the zero signal at the output of the inverter 15 prevents the counter 10 from entering the counting mode. A logical unit signal is generated at the output of the OR element 17 when at least one of the counters 10, 12 is in counting mode and generates a logical unit signal at its output.

The second divider-distributor 11,

0 when a zero control signal arrives from the output of the OR element 17, ignores the clock signal, and the pass from the installation inputs to its output is ignored. the signals from the outputs of the first divider 5 of the distributor 5. When a logical unit arrives at the control input of the second divider-distributor 11, it ignores the signals of the installation inputs, and continues to read the clock pulses, starting from the state (that phase) recorded from installation inputs before the transition of the control signal from zero to one,

In the synchronized mode, when the sampling signals of the frequency divider 3 and the first divider-distributor 5 coincide in time with the responses of the sync group identifiers 1, and there are no errors and signal loss in the communication channel, the analyzers 2 and 6 of the errors generate only correct reception signals . In this case, the decision node 4 is in the synchronism lock mode, the detector 7 is out of synchronism and the trigger 9 is in the reset state, the phasing signal generator 8 does not compare the phases of the frequency divider 3 and the first splitter-distributor 5, counters 10, 12 are stopped and form at their exits

signals of logical zero, resulting in

the phase of the second distributor-distributor 11 all the time coincides with the phase of the first divider-distributor 5 and coincides with the true cyclic phase.

If in the synchronized mode, due to errors in the communication channel, some sync groups appear to be distorted, then error analyzers 2 and 6 give error signals at these moments, and the decision unit 4 can go into synchronism search mode and cause the frequency divider 3 to stop with the first signal errors and run into the account by the first signal of the correct reception. However, in this case, the installation of the divider-distributors 5, 11 is incorrectly extremely unlikely, since this requires the simultaneous fulfillment of two independent unlikely conditions. Firstly, in order to detect a lack of synchronism in the detector 7 of a lack of synchronism, it is necessary that the M synchronization groups of the other are distorted. Secondly, the decision node 4 must fix the incorrect synchronism state, that is, in the information signal in several cycles of the same and at the same cycle positions, signal groups similar to the sync group should be formed. If the detector 7 lack of synchronism does not produce a signal lack of synchronism, then, regardless of the operation of the decision node 4, the shaper 8 fzzzirovaniya signals does not compare the phases of the frequency divider 3 and the first divider - distributor 5, as a result of which the first divider-distributor 5 remains in the correct synchronization mode , and the counter 10 does not start at the same time. If there is no signal loss in the communication channel, then the additional counter 12 is also not started on the account, a logical zero signal is generated at the output of the OR element 17, the second divider-distributor 11 repeats, the output signals of the first divider-distributor 5, and the output signal device corresponds to the true cyclic phase. If the detector 7 lack of synchronism generates a false signal lack of synchronism, and the decision node 4 fixes the correct state of synchronism, then the phaser 8 of the phasing signals compares the phases of the frequency divider 3 and the first divider-distributor 5, and, since in this case they coincide, it only generates a signal at its first output, resetting the detector 7 for lack of synchronism and trigger 9, the phase of the first divider-distributor 5 remains unchanged and corresponds to the true cyclic phase.

If there is no signal loss in the communication channel, then at the moment of the appearance of the signal at the output of the detector 7 of the absence of synchronism, the counter 10 goes into

counting mode, and during subsequent K clock intervals generates a signal of a logical unit at its output. During these K clock intervals, the second divider-distributor 11 is in

0 independent account mode. However, this does not prevent the second distribution divider 11 from being in a state of correct synchronism all the time. Since the phase of the first divider is the distributor 5

5 all the time remains unchanged and corresponds to the true cyclic phase, then the phase of the second divider-distributor 11 cannot be different from the true cyclic phase, at what moment the second divider-distributor 11 goes into self-counting mode, and at what moment he did not go back to the signal repetition mode at his inputs,

If a signal loss occurred in the communication channel that did not lead to a cyclic synchronization failure, then at that moment an additional counter 12 starts up, which for the next L clock intervals is in the counting mode and generates a logical unit signal at its output. During the indicated L clocks, the counter 10 cannot switch to the counting mode if there is no synchronism at the output of the detector 7

5, a lack of synchronism detection signal is generated, and a logic unit signal is present at the output of the OR element 17 during these L clock intervals. .In this case, the second

0, the divider-distributor 11 is in the self-counting mode for L cycles from the moment the signal disappears. However, as in the previous case, this does not lead to a deviation of the phase of the second divider 5 of the distributor body 11 from the true cyclic phase due to the fact that the first divider-distributor 5 is in a state of synchronism all the time.

Thus, the cyclic synchronization device provides high noise immunity for maintaining cyclic synchronization both in the case of non-reception of sync groups due to errors in the communication channel and in the event of a signal loss in the communication channel 5.

Consider the operation of the synchronization device in cycles after synchronization failure. The most likely cause of a cyclic synchronization failure is the failure of the clock system, or the slipping of clock pulses. Such slippage may be caused by interference or signal loss in the communication channel. Slippage can have a different sign: when you skip or the arrival of an extra clock pulse.

If the slip of the clock pulses occurred when there is no signal loss in the communication channel, then in this case the additional counter 12 is stopped and generates a logic zero signal at its output, i.e. additional counter 12 does not take part in the process of restoring synchronism. Conditionally, we believe that the slip of clock pulses occurred inside the 1st cycle. Then, by the end of the Mth cycle, the second error analyzer 6 will generate M error signals from the user. So the detector 7 of lack of synchronism will generate a signal of lack of synchronism at the end of the Mth cycle (with an extra clock pulse) or at the beginning of (M + 1) -th cycle (when skipping a clock pulse). The parameters of the decision node 4 are selected so that by the time of detecting the lack of synchronism, the frequency divider 3 has already found a new state of synchronism, and the decision node 4 has fixed this new state of synchronism and generated a signal at its second output, which prepares the phasing signal generator 8 for phase comparison frequency divider 3 and the first divider-distributor 5. Therefore, a comparison of the phases of the frequency divider 3 and the first divider-distributor 5 occurs at the moment of arrival of the first cyclic pulse of the divider 3 h Toty upon detection of absence of synchronism in the absence of the synchronism detector 7. With an extra clock pulse, the moment of phase comparison corresponds to the end of the Mth cycle, and if the clock pulse is skipped, it corresponds to the end of the (MI) cycle. In this mo-. The moment a new synchronism is established in the first splitter-distributor 5. The counter 10 starts counting when it detects a lack of synchronism, i.e. at the end of the Mth or at the beginning of the (M + 1) th cycle. If the counting coefficient of the 10 K counter is chosen equal to 1.5 cycles (, 5N), then until the middle of the (M + 2) th cycle, the second divider-distributor 11 is in the self-counting mode, and its output signals correspond to the wrong cyclic phase. The final establishment of a new synchronism in the second splitter-distributor 11 occurs when it enters the signal repetition mode at its inputs, i.e. at the end of counter 10, which corresponds approximately to the middle

(M + 2) th cycle. Thus, the moment of the final establishment of a new synchronism in the second splitter-distributor 11 does not depend on the slip sign of 5 clock pulses. This means that the time from the moment of synchronization failure to the final establishment of a new synchronism does not depend on the sign of slippage of clock pulses, but depends only on the moment of failure

0 synchronization inside the first loop. When the information signal is delayed in the receiver in the digital delay line by M + 1 cycle, the maximum time of non-synchronous operation is half

5 cycles, which corresponds to the minimum possible value, when the moment of synchronization failure inside the cycle at the reception cannot be established.

If the clock fails

0 (slipping clock pulses) occurred at the moment the signal disappears in the communication channel, then from the moment the signal disappears and during L clock intervals, the additional counter 12 is in counting mode and generates a logical unit signal at its output. If the synchronization failure occurred in the first cycle, then the first divider-distributor 5 enters a state of new synchronism at the end of the Mth cycle (with an extra clock pulse) or at the end of the (M + 1) -th cycle (when the clock pulse is skipped) . We choose the account coefficient L of the additional counter 12 equal to M + 1 cycles: L (M + 1) -N. Then

5 at the moment of detecting a lack of synchronism (end of the Mth cycle), an additional counter 12 will generate a logical unit signal at its output, preventing the counter 10 from switching to the counting mode. In this case, the signal of the logical element OR will be present at the output of the logic element OR 17 during the counting of the additional counter 12. i.e. during L cycles from the moment the signal disappears. During the indicated L clocks, the second divider-distributor 11 is in the self-counting mode, and its output signals correspond to the wrong cyclic phase. Final moment

0 establishing a new synchronism in the second splitter-distributor 11, respectively. corresponds to the moment of transition of the second splitter-distributor 11 to the signal repetition mode at its inputs and determines 5 with the moment of completion of counting of the additional counter 12, which is inside the (M + 2) -th cycle exactly after the M + 1 cycle from the moment the signal disappears. Since the moment of synchronization failure corresponds to the moment of signal loss,

then my synchronization failure inside the first loop is actually known at the reception. The time from the moment of synchronization failure to the final establishment of new synchronism in the second splitter-distributor 11 is equal to L clocks (M + 1 cycles) and does not depend on either the slip sign of the clock pulses or the moment of synchronization failure inside the first cycle. When the information signal is delayed in the receiver in the digital delay line by M + 1 cycle, the time of non-synchronous operation after the disappearance of the signal does not exceed the duration of the signal loss. For short-term dips, this time is short compared to the cycle time.

Claims (1)

SUMMARY OF THE INVENTION Cyclical synchronization device containing a sync group identifier, the output of which is connected to the first input of the first error analyzer, the second input of which is connected to the output of the frequency divider, and the outputs of the first error analyzer are connected to the corresponding inputs of the frequency divider. the synchrogroup through the second analyzer is connected to the inputs of the detector of lack of synchronism, the output of which is connected to one of the inputs of the trigger, the output of which 1 is connected to the input of the first raster divider - a limiter through a phasing signal shaper, the other inputs of which are connected respectively to the outputs of the deciding node of the frequency divider and the first splitter-distributor, and the other output of the phasing signal shaper is connected to the reset inputs of the lack of synchronism detector and trigger, and the control input of the second error analyzer 10 is connected to the output the first divider-distributor, the clock input of which is the clock input of the device and connected to the clock inputs of the frequency divider, counter and second a divider -ras15 predelitel, installation whose inputs are connected to respective outputs of the first divider -raspredelitel, characterized in that, in order to reduce the time synchronism upon reduction 20 signal failures, an OR element is introduced and an amplitude detector, a threshold block, an additional counter, an inverter and an NAND element are connected in series, while the detector output has no synchronism 25 is connected via an AND-NOT element to the control input of the counter, the output of which is connected to the control input of the second distributor-distributor through the OR element, the other input of which is connected to the output of the additional counter, the clock input of which is connected to the clock input of the counter.