SU1529205A1 - Device for synchronizing a computing system - Google Patents

Abstract

The invention relates to computing and can be used in the construction of computing systems. The device allows control of time signals. The aim of the invention is to increase the reliability of the operation. The goal is achieved by the introduction of the element OR 13, the elements AND 7,8,18, triggers 10,11. 2 Il.

Description

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The invention relates to computing technology and can be used in the construction of computing systems.

The aim of the invention is to increase the reliability of the operation.

FIG. 1 shows a diagram of the device; in fig. 2 - time diagram of his work.

The device contains a distributor of 1 pulses, a counter 2, a decoder 3, the first - the fifth elements AND 4-8, the first - the third triggers 9-11, the first 12, the second 13 elements OR, the input 14 signals of the exact time of the device, the clock output 15, the output 16 sign of the presence of signals of the exact time of the device, the output 17 of the sign of the mismatch, the sixth element And 18, asked, the generator 19.

FIG. Figures 1 and 2 show the following designations of the inputs and outputs, as well as the signals on them: C, C - the first and second outputs of the distributor 1 of pulses, K - group of outputs of the counter 2 and inputs of the decoder 3, NMHH ,, NHO ", Nnt-p ,, Ymak. No - outputs of the decoder 3, respectively, the fixed minimum, nominal, transient, maximum, zero values of counter 2; M-signals of great time, arriving at the input 14 of the device; t is the control time interval (in the counter 2 operation cycle) for receiving signals; M exact time.

The device works as follows.

The device outputs from the output 15 control signals generated depending on the modes of its operation; from the signals of the exact time of input 14 - when the device operates synchronously with these signals or from the signals NwaK., N MM, Nnep, respectively, in the absence of the first signal of the exact time, during the subsequent operation of the device without accurate time signals and in the device subsynchronization mode with accurate time signals.

The distributor 1 pulses forms shifted but phase relative to each other sequences C and C clock pulses, arriving respectively at the counting C and at the input element And 18.

Counter 2 conducts a cyclic counting of the impulses within the period of the signals of the exact time from zero to some value (Nmn., NHOM ,, NIR-P, Ymak,), prior to its installation in the "O" by coincidence of the control signal from the output 15 I- clock pulse.

At the output of the OR 13 element, a signal is generated that determines the allowable time interval t for receiving the time signal from input 14. This interval is formed from the time intervals of the end of the current and the beginning of the next 2 counter cycles (from signals

, NHOM, Nncp., NMBK ,, No, from the corresponding outputs of the decipher 3). Below to clarify the operation will be considered a device with the following parameters;

the period of the signals of the exact time is 1 ms, the frequency of the master oscillator is 252 kHz with a maximum permissible relative error of 10

When an exact time signal M arrives at input 14, trigger 10 is set to " O, at output 16 an indication of the presence of an accurate time signal appears. If the incoming signal M is within the interval t, then through the element 4 it sets the “On the flip-flops 9, 11 and

5 element AND 7, OR 12 is fed to output 15 as a control signal. At the output 17, there is no indication that the device is not synchronized with the time signals; device works .. melts in synchronous operation mode.

In the presence of accurate time signals, counter 2, before being reset to the zero state, in most cases assumes the nominal (N liov.) Value, in the given trigger - 252 cycles. As the time error is accumulated from the frequency error of the master oscillator, depending on its sign, cycles are periodically formed with a reduced or increased final value of counter 2, which depends on the frequency (Lg) of the master clock.

generator 1, its relative error (a) and the duration of the period (T) of the signal. The exact time - of the cycle duration - “. Counter 2 is working. The maximum possible time error (tiiDip.) in the account arising from the frequency error the generator and the time signal accumulated over one period can be calculated (in cycles) as follows; troip a T. When accepting the boundary values of the time interval ujHpe (or equal to) the possible error in the clock count for the period of the signal M of the exact time, the leading edge and the beginning of this signal will always fall into the specified interval and arrive at the clock output 15, those. It is possible to form time intervals with an accuracy of the arrival of signals M at input 14 and not dependent on faults of the master oscillator 1. Therefore, the lower limit of interval 1 will be the value of. counter 2 away from nominal

NHOM values. at least tnorp, calculated for the specified formula. The increased in comparison with N HOSI., Final value of counter 2 in the period of the signal M is also taken as the value of the transition (Chur.) Period of control signals at the output 15 in the sub-synchronization mode of the device.

For the given example, the value tnoir. will be 0,252 bars, the poet value

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NMHH, Nncp will differ from the NHOM value by no more than 1 cycle and correspond to 251 and 253 counter cycles.

The clock pulse C is asynchronous with respect to the signal at the output 15, may coincide with its leading edge and immediately reset the counter 2 to the zero state. Therefore, to extend the pulse at the output 15, the signal No decryption of the zero state is included in the automatically regulated interval t the counter 2. Before the counter 2 is removed, the zero state (on the first pulse C in the next cycle of operation) is allowed to transmit the signal M from input 14 to output 15, thereby guaranteeing a certain minimum duration of the output control signal.

If the input 14 of the first exact time signal fails, counter 2 gets the ability to count impulses C from the master oscillator to the maximum (NvaK) value, for example, up to 254 clocks. Thereby, the triggers 10 and 11 are set to 1, the sign of the presence of a time signal is removed at the output 16, and at the output 17 there appears a sign of non-synchronization of work with the signals of the exact time. The signal. Mac through the element OR 12 enters the output 15,

Starting from the next cycle after switching on the trigger 11, the device autonomously generates control signals with a cycle of nominal duration, for example, 252 cycles with an error of the distributor 1 pulses, by issuing signals from the N.I04 output, decoder 3 through AND 5, OR 12 to exit 15.

When a signal M of precise time appears at input 14, trigger 10 is set to " O, output 16 and element 8 of the first input 8 indicates that there is a time signal.

If the incoming signal is within time interval 1, then the device enters the described synchronous mode of operation.

When the device is out of sync, i.e., if the signal t does not match the signal M at the inputs of element 4, its passage to output 15 is forbidden, the trigger 11 continues to remain in one state, and the output setting element 8 appears 9 in a single state. In this case, the signal from the inverse output of the trigger 9 prohibits the passage of NHOM signals, through element 5 to output 15, counter 2 is able to count to a value Nm-p equal to, for example, 253 cycles, the corresponding signal from the output of decipher 3 through elements 6 , OR 12 will hit output 15, i.e., the device starts to play control signals with an extension

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This period is included in the sub-sync mode.

This mode, m, continues until synchronization in the output of control, signaling signals; 1s with the signals M of the exact time at input 14 is achieved.

When hit1 1; C-channel in interval 1, the device goes into synchronous mode of operation, while the passage of signals NHOV, and Ni: c; .. through the elements And 5, And 6 is prohibited, the output 15 again receives the signals M from input 14

FIG. 2 shows a timing diagram of the operation of ycTpoiiCTBa in the described modes and showing synchronous operation with an accurate time signal M; work with OTcyTCTBHii of the first signal, 1a M; subsequent work without the arrival of signals M; subsynchronization of tsnk) device when the asynchronous L1 signal is generated. After reassuring the device, the device again works in accordance with the time diagram a.

If the calculated deviation of the possible deviation (1: k.gr) from the nominal value (NHOV) of the value in the counting of the signals C of the counter 2 exceeds the values of the 1st period of the master oscillator (for example, If the difference between the frequencies of the master oscillator 1 and the M signal is of the exact time, or a large relate, 1 error of the master oscillator), then counter 2 may have an additional frequency divider. The output signal is C | with iodiod.m equal to nosko, 1ki, 1, HaiipiiMefi 2, 4, and t, e., periods of signal C, i.e., the period of input signal for the main divide, t frequencies, is lengthened. In this case, the first divider. May not have installation inputs in "O. Thus, the device will operate with an increased period of time of the signal from the master oscillator in accordance with the time diagram described (Fig. 2), where the role of signal C is to carry out signal C.

Formula of invention

Device d: 1 synchronization of the computational system. We contain the master generator, the counter, the decryptor, the first trigger, the first, second and third elements AND, the first element OR, the output of the first element OR V, 1 is not the clock output. device, the group of outputs of the counter is connected to the rpynnoi i information inputs of the decoder, the first output of which is connected to the first input. The first, 1st, third OR, the second and third inputs of which are connected respectively to the outputs of the second and third electrons And, my first output of the first trigger is connected to the first input of the third element, And the second input is connected to the second terminal of the depumer . The first input of the first element I is the signal input signal of the exact time of the device, characterized in that, in order to increase the reliability of the operation, the second element OR, the fourth, fifth and sixth elements AND, the second and third triggers and the pulse distributor are entered into the device, moreover, the output of the master oscillator is connected to the clock input of the pulse distributor, the first output of which is connected to the counting input of the counter, the first input of the second OR element is connected to the input of the installation in “1 second trigger and the first output d the encoder, the second, third and fourth outputs of which are connected respectively to the second, third and fourth inputs of the second OR element, the fifth input of which is connected to the fifth output of the decoder and to the first input of the second element And, the second input of which is connected to the inverse output of the first trigger, the output of the second element OR is connected to the second input of the first element AND, the output of which is connected to the reset inputs in “About the first, third triggers and

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The fourth input of the AND element, the output of which is connected to the fourth input of the first OR element, the reset input of the second trigger, is the input of the device’s time signal, the inverse output of the second trigger, and the output of the sign of the presence of signals the exact time of the device, the output of the fifth element And is connected to the single input of the first trigger, the second input of the fifth element And is connected to the third input of the second element And, the direct output of the third trigger and is the output recognized a device mismatch, a direct output of the second flip-flop coupled to the input for setting "1 third flip-flop, the second output pulse distributor coupled to the first input of the sixth AND gate, a second input coupled to an output of the first OR gate. output niecToro element And is connected to the input. iOM reset in “About the counter, the inverse output of the third trigger is connected to the second input of the fourth element I.

Claims (1)

For ul and zobreten A device for synchronizing a computing system containing a master oscillator, counter, decoder, first trigger, first, second and third AND elements, the first OR element, the output of the first OR element being the device’s clock output, the group of counter outputs connected to the group of decoder information inputs, the first the output of which is connected to the first input of the first OR element. the second and third inputs of which are connected respectively to the outputs of the second and third elements I. The direct output of the first trigger is connected to the first input of the third element I. the second input of which is connected to the second output of the desichrrator. the first input of the first AND element is an input of accurate time signals of the device, characterized in that, in order to expand the reliability of operation, the second OR element, the fourth, fifth and sixth AND elements, the second and third triggers and the pulse distributor are introduced into the device, moreover, the output of the master oscillator is connected to the clock input of the pulse distributor, the first output of which is connected to the counting input of the counter, the first input of the second OR element is connected to the installation input in “1” of the second trigger and the first output the encoder, the second, third and fourth outputs of which are connected respectively to the second, third and fourth inputs of the second OR element, the 15th input of which is connected to the fifth output of the decoder and the first input of the second element And, the second input of which is connected to the inverse output of the first trigger, the output of the second element OR connected to it with the second input of the first element I. the output of which is connected to the reset inputs at “0” of the first, third triggers and the first input of the fourth element AND, the output of which is connected to the fourth input of the first about the OR element, the reset input at “0” of the second trigger is the input of the device’s exact time signal, the inverse output of the second trigger is connected to the first input of the fifth element And is the output of the sign of the presence of the exact time signals of the device, the output of the fifth element And is connected to the unit input of the first trigger , the second input of the fifth element And is connected to the third input of the second element And, the direct output of the third trigger and is the output of the sign of mismatch of the device, the direct output of the second trigger is connected to the input set Saw "1" of the third trigger, the second output of the pulse distributor is connected to the first input of the sixth AND element, the second input of which is connected to the output of the first OR element. the output of the sixth element AND is connected to the reset input at “0” of the counter, the inverse output of the third trigger is connected to the second input of the fourth element I. but AND 8 from || | ffii | from' ........ F f f f f f f f f Sch1 Poison; N _min N _nvm Nftim Rg; 1 f ι ί. V K. ι G f 1 1 ί 'χ t . 177777777777771 „ΤΓ7777777Γ7Τ77ΤΠ \ .. Tgu 1 g AND I (Z- ...... 1 1 „7777777777 Tg // 'ι j A ............. L 1 ,, 1777777771 " Tg 9 ¹ ι L 'ι ι: . ....... ^ 77/7 // ^ _H Wf 8 m .. 7777777 from It Tro 1 t t 1 / from It 1 1/1111 Si 2 R * uh Ro 1: Rmuh N _ho „ti _o 1 ι ι,, ¹ I ^{- 1 1 1} iii" t Τζ! Ϋ́ 777777777 ^ 777777 / ,, / 71 '1 1 Tg // 77777777777777777777 ^^ 77777777 / / 7/77 // 7 /// 777Ά> Tg 3 1 1 1777777777 // ////// 7 // Out. 15 fezzL, μ ___________