SU1218462A1 - Phase-lock loop - Google Patents

Abstract

This invention relates to electro. connection and m., used in automation and telemechanics, the phasing accuracy is increased without reducing the synchronization band. The device contains the 1st element AND-NOT 1, the 1st delay element 2, the 2nd delay element 3, the 2nd element AND-NOT 4, the phase detector 5, the low-pass filter 6 and the controlled oscillator 7, Enhance precisely Phasing without reducing the synchronization bandwidth is achieved by the fact that between the output of the controlled oscillator 7 and the input of the 2nd element, AND-NO 4, the 1st element of the delay 2 and between the output of the 1st element AND-HE 1 and the other input 2 of the 4th element of AND-NE 4, the 2nd element of delay 3 is turned on, and the other input of the 1st element of AND-NOT 1 is connected to the output of the controlled oscillator 7, and the phase mismatch is determined by the duration of the pulses at the output of the 1st element AND-NOT 1. As the duration of the synchronizing pulses increases, the duration of the pulses at the output of the 1st element AND-NOT 1 automatically decreases. As a result, the dynamics of the phase detector 5 does not change, but the zone of uncertainty remains constant, depending only on the magnitude of the delay. The proposed device ensures normal operation at a multiple ratio of frequencies, t, e. with an extended range of synchronization frequencies, 4 Il. five

Description

The invention relates to telecommunications and is intended for use in digital communication systems to provide synchronous operation of receiving and transmitting equipment, and can also be used in automation and telemechanics.

The aim of the invention is to improve the phasing accuracy without reducing the synchronization band.

.1 presents the structural electric circuit of the device for synchronization with PAL; Fig. 2 shows timing diagrams illustrating the operation of the device in a state of dynamic equilibrium for the case of fj.f () and the duty cycle of synchronizing pulses, taking into account the inertial properties of the elements of the temporal detector fc and ff, respectively, the signal frequency and the controlled generator; FIG. 3 are timing diagrams illustrating the operation of the device in the internal synchronization mode, i.e. in the absence of a synchronizing signal; figure 4 - timing diagrams illustrating the operation of the device for the case

N

| ..

L. Tc .2

is

The FAL device contains the first AND-1 element 1, the first 2 and second 3 delay elements, the second AND-NOT 4 element, the phase detector 5, the low-pass filter 6 and the controlled oscillator 7.

The device works as follows.

Input clock pulses (Fig. 2, a) are fed to one of the inputs of the first element AND-NO 1, to the other input of which the pulses (Fig. 2, e) are drowned from the controlled generator 7.

When these pulses coincide, impulses (Fig. 2, b) pass through the first element AND-NOT 1 to one of the inputs of the phase detector 5. At time t, coinciding with the moment of arrival of the pulses (Fig. 2, b) from the first element I-NOT 1, the phase detector 5 through the response time delay tp switches from zero to one (Fig.2, g), in which it remains until the moment t arrives pulses (Fig.2, d) from the second element /

That AND-NOT 4. On one of the inputs of the second is 218462. 2

The second element AND-NOT 4 receives pulses (FIG. 2, c) from the first element AND-NOT 1, which are delayed by the amount and sorted by the second 3 delayed delays. At the other input of the second element AND-NOT 4, pulses arrive (Fig. 2, d) from the controlled gam-. nerator 7, delayed by the value of i.

ten

IS

first element 2 delay. pulse arrival

one

At time t

From the second element NAND 4 to the input of the phase detector 5, it is decided to switch it from one state to another. The decision to switch the phase detector 5 and, therefore, to correct the controlled oscillator 7 is made depending on

45

55

availability (with a pulse duration of i L in iv. at which the phase detections f ih

thirty

35

20 torus is capable of switching to a different state of pulses (Fig. 2, d) from the second element AND-NOT 4. The presence or absence of pulses at the output of the second element AND-HE 4 is determined

25; phase (time) mismatch tp of the pulses at the inputs of the phase detector 5. In the state of dynamic equilibrium, the phase mismatch (error) changes from the maximum value (cooTBeTCTBy Qin, ero presence of a pulse at the output of the second element AND-HE 4) to the minimum value (no pulses at the output of the second element AND-NOT 4).

  depends on the frequency detuning, is determined by the insensitivity of the time detector.

Due to the finite value of i RJ, the fronts of the pulses (marked with a dotted line in Fig. 2) are subject to jitter with a sweep determined by the value of tgj,.

From the analysis of the time diagrams of Fig. 2, it follows that the values of the delays t, and 1 must be selected from the condition that there are no overlap of pulses at the inputs of the phase detector, which is performed if; the value of L is bounded from above by the condition of ensuring the duration of the pulses at the output of the first AND-NE 1 element, sufficient for a stable transfer. one

l BUT.

, 1g and

performed in practice), then in a state of dynamic equilibrium it sets 40

50

phase detector, .t, .t

Thus, if t. i. 1 -i-oih these conditions are easy

31

with such a mode of operation of the time detector, in which the pulses of the controlled oscillator (Fig. 2, e) are connected to the leading edge C1} of the synchronizing pulses, which does not lead to a change in the phase error and the uncertainty zone Ic of the phase detector.

The magnitude of the phase mismatch

(r, -, + rn, r; „. l; rn, n; ,,„) is determined herewith by the duration of the pulses at the output of the first AND-NO element 1.

Indeed, with an increase in the duration of the synchronizing pulses (LUC s), the pulse duration (LMC s) and the output of the first AND-NE unit 1 are automatically reduced, and as a result, the dynamics of the phase detector 5 does not change, and the uncertainty zone () -t 2+ CKJ) remains constant, depending only on the amount of delay t.

Thus, an improvement in phasing accuracy is achieved without reducing the sync band.

When the synchronizing signal disappears, it automatically switches to the internal synchronization mode (autogeneration) at the nominal frequency.

If the synchronization signal disappears (breaks the input circuit), i.e. in the presence of a single potential (Fig. 3, a) at the input of the first element AND-NOT 1, pulses arrive at the first input of the phase detector 5 (Fig. 3, BT from the controlled generator, (Fig. 3, e).

Pulses (Fig.3, 6) from the first element AND-NOT 1, passed the second delay element 3 (figure 3, c) through time Lj. The input of the second element is NOT 4. The other input of this element receives pulses from the controlled oscillator (Fig. 3, e), delayed by the time L by the first delay element 2 (Fig. 3, d). Since the pulses (Figures 3, b and 3, d) enter the second element AND-NO 4 almost simultaneously with Ct - n), they pass through the 3Tot element and enter the other input of the phase detector 5.

The phase detector 5 switches to the one state with the arrival (t) of the pulse from the first element AND-NOT 1

218462

and returns to the zero state with the departure (t3) of this pulse. Switching at the moment t of arrival of the pulse (Fig. 3, g) to the second input of the phase 5 detector is impossible due to the presence of a pulse (Fig. 3.6) at its first input. In this case, the phase de. tector 5 performs the functions of a pulse inverter (FIG. 3, g) arriving 10 at its input from the first element

I-NOT 1. When the duty cycle of these pulses is equal to two, the control voltage generated by the low-pass filter 6 from the signal of the phase detector 15 takes the average value (Fig.3, d dotted line) and the generator 7 provides the generation pulses with a nominal following frequency, corresponding to zero frequency 20 detuning.

In the known synchronization devices using two-position time detectors, this positive property is absent, 25 since the phase detector, when the synchronization signal disappears, switches to one stable state corresponding to a positive or negative maximum HF frequency detuning.

The proposed device ensures normal operation at a short frequency ratio both at fc fg and at fc fp, i.e. with

35

extended range

synchronizing frequencies.

4 shows timing diagrams illustrating the operation of the device with a positive (in Q 4 on the left) and negative (in FIG. 4 on the right) maximum frequency detuning.

In contrast to the case (f (. "Fr), the operation of the phase detector here is influenced by interfering pulses (shaded in Fig. 4), which pass through the first element AND NOT 1 (Fig. 4, b), the second element 3 delays (Fig. 4, c) and the second element IS-HE 4 (Fig. 4, d). As a result, the phase detector 5 switches from one state to another, regardless of the magnitude and sign of the phase mismatch, and is in this state on the duration of these interfering pulses.

However, this does not disrupt the operation of the device, since at the time the phase detector 5 switches to 50

55

extended range

synchronizing frequencies.

Figure 4 presents timing diagrams illustrating the operation of the device with a positive (in figure 4 left) and negative (in figure 4 right) maximum frequency detuning.

In contrast to the case (f (. "Fr), the operation of the phase detector is affected by interfering pulses (shaded in Fig. 4), which pass through the first AND-NE 1 element (Fig. 4, b), the second delay element 3 (Fig. 4, c) and the second element IS-HE 4 (Fig. 4, d). As a result, the phase detector 5 switches from one state to another regardless of the magnitude and sign of the phase mismatch and is in this state for the duration x these interfering pulses.

However, this does not disrupt the operation of the device, since at the time the phase detector 5 switches

In the initial (single) state, and after time L at time 12 it is decided to switch it depending on the phase mismatch of the synchronizing pulses (Fig.4, a) and the pulses of the controlled generator 7 (Fig.4, e and 4, e) As in the case, when the pulse duration at the output of the second element IS-HE 4 is sufficient for stable switching of the phase detector, the latter switches to the zero state (in Fig. 4, left).

With a pulse duration of l rr

at the output of the second element AND-NOT 4, the phase detector 5 remains in the single state (in Fig. 4 on the right). After a time equal to the period following the pulses Tp, the picture repeats again. Thus, here the influence of interfering pulses only leads to y. the increase in the zone of uncertainty of the phase detector 5 by the value of Lcd, i.e. to a decrease in the control voltage (Fig. 4, f to the right of the dotted line) and an increase in Uy t (Fig. 4, w to the left of the dotted line). The reduction of the synchronization band by reducing the magnitude of the control voltage is insignificant, (in this case

with t in

. i: tea 1- 0,815) and weakly for-T g

depends on N, since with an increase in N although the uncertainty zone increases, however, the period of regulation of Tr increases proportionally.

to

Form la invention

A phase locked loop device containing the first NAND element connected in series, one input

which is the input of the device, a phase detector, to the other input of which a second NAND element is connected, a low-pass filter and a controlled oscillator, characterized in that, in order to improve the phasing accuracy without decreasing the sync band, between the output of the controlled oscillator and one input of the second element is NOT included

the first delay element, between the output of the first NAND element and the other input of the second NAND element, the second delay element is switched on, while the other input of the first NAND element

connected to the output of the controlled generator.

FIG. 2

Claims (1)

Yu claims A phase-locked loop device containing the first AND-NOT element in series, one input 15 of which is the input of the device, a phase detector, the second AND-NOT element, a low-pass filter and a controlled oscillator connected to the other input, distinguishing 2Q with the fact that, in order to increase the accuracy of phasing without reducing the synchronization band, between the output of the controlled generator and one input of the second AND-NOT element, the first delay element 25 is turned on, between the output of the first AND-NOT element and the other input of the second element AND-enabled vtoroy'element delay, the other input of the first AND-NO element is connected to the output 3Q controlled oscillator. . Wr “It ^ ί / C P b πι W 1 ^τ ζ 8 -------- m W t'niin „ g ___ φ ____ W d 1 1 Η ¹ ιίι 1 i Tf e ! ϋϊ _: g ----------: .......— Έηο 1 F __1____ Γ ’ 1 ι. 1-- ί 1 1 I tcmox tcmin FIG. 2 12184'62 [Ί t _s P 1 X ^isp η p b 1 ............. m G th Τί n P 1 ty ^ ^{t, n} I Tur __ΓΊ — ΓΊ ΓΊ Π ... Π,> / __ ~ <ir -................ rir ^, --- ίφ Π, ----- Π __ Ж1Г _t = 3L mm e f --- f-te / isip rio fczi c t _t t ₂ t FIG. 4