SU544160A1 - Cycle sync device - Google Patents

Description

a clock has been sent to the control input of which and the corresponding input of the frequency divider, an additional error analyzer, a synchronism detector, a phasing signaling amplifier and a trigger have been entered, the synchrogram identification output is connected to the inputs of the absence of synchronism through an additional error analyzer, the output of which is connected to one of the trigger inputs, the output of which is connected to the input of the splitter distributor via a phasing signal generator, to other inputs which give reschayuschego node outputs are connected respectively, and frequency divider -raspredelitel divider and its output - to the reset inputs of a detector absence sinhro1tazma and trigger, with a further control input connected to the output mismatch error analyzer -raspredelitel divider.

The drawing is a structural electrical circuit diagram of a cycle synchronization device.

The proposed device contains a sync group identification 1, the output of which is connected to the first input of the error analyzer 2, the second input of which is connected to the output of frequency divider 3, the outputs of analyzer 2 error connected to the corresponding inputs of frequency divider 3 directly and through decisive node 4, as well as distributor 5, to the control input of which and to the corresponding input of frequency divider 3, clock pulses, additional analyzer 6 faults, detector 7 no synchronism, shaper 8 signal phasing and trigger 9, while the output of the sync group identifier 1 is connected via an additional analyzer in the faults to the inputs of the missing synchronizer 7, the output of which is connected to one of the inputs of trigger 9, the output of which is connected to the input of the splitter distributor 5 through the phaser 8, to the phasing signal other inputs, which are connected respectively to the outputs of the deciding node 4, frequency divider 3 and distributor divider 5, and its output to the reset inputs of the detector 7 without synchronization and trigger 9, and To the control input of the additional analyzer 6 error, the output of the distributor-distributor 5 is connected.

The device works as follows

The received digital signal arrives at the sync group identifier 1, at the output of which signals are generated both on the sync group and on the code groups of the information signal, similar to the sync group.

The signals allocated by the cognizant of the 1 sync group are fed to the input of the analyzer 2 chips and to the input of an additional analyzer 6 errors. In addition, analyzer 2 receives a test signal from frequency divider 3 and additional analyzer 6 errors from the distributor distributor 5. The signal of the correct reception of the response of the synchronizer group 1 to the sync group and the error signal are received from the analyzer's output 2 error to the inputs of frequency divider 3 and Decisive node 4, which, with low inertia, detects a lack of synchronism and resolves the correction of frequency divider 3 in the search for synchronism. The same node ensures the fixation of the state of synchronism and the preparation of the phasing signal generator 8 for comparing the phases of frequency divider 3 and distributor dividers 5.

The output signal of the missing synchronism detector 7, to the input of which the correct reception signal is received and the error signal from the output of the additional analyzer 6 error, the trigger 9 is set to prevent the phase divider 3 and the distribution distributor 5 in the driver 8 phase signals.

If there is a sync signal failure in the established mode, that is, until the moment when the inertial absence synchronization detector 7 detects a lack of synchronism, both analyzers 2 and 6 are faulty, depending on whether the sync 1 identifier responds at the time of testing or not, reception or signal error. In this case, the decisive node 4 can detect lack of synchronism with low inertia, as a result, a signal is generated allowing control of the frequency divider by 3 signals from the output of the analyzer 2 error (i.e. the frequency divider 3 is stopped by the first error signal and the start is by correct reception signal).

After the synchronization state is fixed by the decisive node 4, a signal is formed in this node that ensures the non-stop operation of frequency divider 3, as well as a signal that prepares the driver 8 for the phasing signals. In this case, if there is a locking of the synchronization state, it does not affect the operation of the device in any way, since the phasing of the receiving distributor 5 in this case does not occur.

Claims (2)

When synchronization is violated, the inertia detector 7 a lack of synchronism and the decisive node 4 start detecting the absence of synchronism. At the same time, while the inertial detector 7 out of synchronism detects a lack of synchronism, the decisive node 4 will have time to detect a lack of synchronism with low inertia and, together with frequency divider 3 and analyzer 2 errors, provide for the search and fixation of a new state of synchronism. After the absence of synchronization is detected, the trigger 9 switches to the position allowing the shaper of the phasing 8 signal to compare the phases of frequency divider 3 and splitter divider 5. In case of phase divergence of frequency divider 3 and splitter divider 5, a signal is generated in the phaser 8 of the phasing signal the phases of the splitter 5 in accordance with the phase of the frequency splitter 3, and also a signal is generated that triggers the reset of the trigger 9 and the inertial detector 7 without synchronism. When the phases of the frequency divider 3 and the distributor distributor 5 coincide, the phasing signal generator 8 generates only one signal, which triggers the trigger 9 and the missing synchronizer 7. The invention includes a cycle synchronization device containing a sync group identification at the input, the output of which is connected to the first input of the error analyzer, to the second input of which the output of the frequency divider is connected, and the analyzer outputs of the error are connected to the corresponding inputs of the frequency divider directly and through the decisive node, as well as the divider -distributor, to the control input of which and to the corresponding input of the frequency divider clock pulses are supplied, characterized in that, in order to reduce the time of entry into Inchism and noise immunity, a complementary error analyzer, a missing synchronization detector, a phasing signal generator and a trigger were introduced, and the sync pattern identification output was connected via an additional error analyzer to the missing synchronization detector inputs whose output is connected to one of the trigger inputs whose output is connected to to the input of the splitter distributor through the phasing signal generator, to the other inputs of which are connected the outputs of the decisive node, respectively a, a frequency divider and a distributor distributor, and its output - to the reset inputs a missing synchronizer and a trigger, and to the control input of the additional error analyzer the output of the distributor distributor is connected. Sources of information taken into account in the examination: 1. Martynov E. M. Synchronization in systems for the transmission of discrete messages, M., Sv, communication, 1972 p. 126. 2. The patent of Germany No. 1142921 cl. 21, 1963 (prototype).