SU1670794A1 - Device for determining validity of binary information transmission - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to enhance the functionality by providing an estimate of the dispersion and width of the spectrum of phase fluctuations. The device contains a test signal sensor 1, including a clock pulse generator 1.1 and a test signal driver 1.2, a reference element 2, a control signal sensor 3, prohibition elements 4, 5, a clock synchronization system 6, a coincidence element 7, a cycle marker generator 9, a cycle trigger 9 phasing, 10 affected cycles indicator, delay elements 11, 12, 13 clock pulse generator, phasing indicator 14, integrator 15, block 16 counters, delay line 17, pulse width controller 18, mismatch detector 19, kstremalny controller 20, the control unit 21, the selector 22, the duration of the pulse series and computing unit 23, the channel 24 communication. Blocks 1–15 isolate errors in binary information to determine the reliability of its transmission, and interacting with them blocks 17–22 to determine the variance and width of the spectrum of phase fluctuations. Based on the results recorded by block 16, block 23 calculates the transmission quality characteristics. 1 il.

Description

one

(21) 4642888/09

(22) 26 „12„ 89

(46) 15008091, Bul „ЗС

(71) Leningrad Electrotechnical, g: - cue institute of communication im prof, i. / S wonch-bruev

(72) V.ES Gurevich, E „Я0 Durets and Likontsev

(53) 621.394.62 (088.8)

(56) USSR Copyright Certificate No. 274152, cl. H 04 L 1/00, 1967,

(54) DEVICE FOR DETERMINING THE RELIABILITY OF TRANSMISSION OF BINARY INFORMATION

(57) The invention relates to telecommunications. The purpose of the invention is to expand the functional potential of the gay by providing an estimate of the dispersion and spectral width of the phase fluctuations. The device includes a test signal sensor 1 including a clock pulse generator 101 and a 1: 2 test signal driver, element 2 comparisons

pilot signal sensor 3, prohibition elements 4, 5, clock synchronization system 6, coincidence element 7, cycle mark generator 8, cycle phasing trigger 9, affected cycle indicator 10, delay elements 11, 12, clock pulse generator 13, phase indicator 14 integrator 15, counter 16 block delay line 17, pulse duration regulator 18, mismatch detector 19, extreme regulator 20, control block 21, pulse train duration selector 22 and calculation block 23, communication channel 24 Blocks 1-15 select errors in binary information for determining the reliability of its transmission, and interacting with them blocks 17-22 for determining the variance and spectral width of phase fluctuations. Based on the results recorded by block 16, block 23 calculates the characteristics of the transmission quality. 1 silt

S

V

WITH

vj

about i

2

The invention relates to telecommunications, can be used to control the parameters of regenerators and digital linear paths in communication systems with pulse-code and delta modulation

The purpose of the invention is to enhance the functionality by providing an estimate of the dispersion and spectral width of phase fluctuations.

The drawing shows a structural electrical circuit of the proposed device,

A device for determining the accuracy of binary information transmission includes a test signal sensor 1, which includes an I ' 1 clock pulse generator and a test signal generator 10, a comparison element 2, a pilot signal sensor 3, prohibition elements 4 and 5, a clock synchronization unit 6, match element 7, cycle mark generator 8, cycle phasing trigger 9, 10 affected cycles indicator, delay elements 11 and 12, 13 clock pulse generator, phase indicator 14, integrator 15, block 16 counters, line 17 delays, pulse duration controller 18, mismatch detector 19, extreme controller 20, control unit 21, pulse train duration selector 22 and calculation unit 23, communication channel 24 ,.

The device works as follows

The test digital signal produced by the sensor 1 of the test signal is transmitted through the communication channel 24 (a generator) to the second input of the comparison element 2, to the first input of which the reference signal generated by the control signal sensor 3 is started. after establishing synchronism between them, provided by block 6 of clock synchronization and blocks 7-15, performing cyclic synchronization Digital errors, highlighted by comparison element 2, are counted by block 16 counter Clock pulses in the generated clock unit 6 from the incoming signal, and therefore susceptible to fluctuations in phase are supplied to the input of the non-coincidence detector 19, the other input of which is supplied by a generator of clock pulses K1, WMOs

0

Q, -

five

0

five

For example, in the sensor 1 is a test signal, a sequence of clock pulses through a controllable delay line 17 and a pulse duration regulator 18. The delay can be set manually or using an extreme regulator 20 to minimize the number of mismatch pulses.

The mismatch pulses extracted by the discrepancy detector 19 are recorded by a block of 16 counters. The number of mismatch pulses is determined by the variance of the phase fluctuations of the test digital signal transmitted through the test communication channel 24 (regenerator) during the measurement session. “In addition, at the output of the detector 19 there are discrepancies by the selector 22 of the duration of a series of pulses synchronized by pulses of the clock frequency from the output of the regulator 18 lnosti pulses are allocated a series of pulses having a duration set by a control unit 21, which unit 16 are recorded on the counter number of series of a certain duration measurement session characterizes the width of the spectrum of the phase fluctuation "Calculation of probability error variance and the spectral width of the phase fluctuation is produced in the calculation block 23

Thus, the transmission quality of a digital linear path is estimated not only by the number of digital errors at its output, but also by parameters such as the dispersion and spectrum width of the phase fluctuations of a digital signal at the output of a digital communication channel.

The proposed device can determine the accuracy of the transmission of a digital signal, both by ilef and by. direction, and the statistical characteristics of the phase fluctuations only on the loop, because the controllable delay line 17 is connected to the clock output of the test signal sensor 1, which is on the transmitting side. If the controllable delay line 17 is connected to the output instead of the clock input of the test signal sensor 1 clock generator 13 located at the receiving end of the communication channel 24, it is possible to estimate the quality of the digital signal transmission as

However, due to the imperfection of the 13-clock pulse generator, part of the phase fluctuations is transmitted from its input to the output, with the result that with such a connection the accuracy of estimating the statistical characteristics of the phase fluctuations „

Claims (1)

Invention Formula one A device for determining the reliability of binary information containing a test signal sensor whose information output is an input of a communication channel, a serially connected unit such as synchronization HIT, a clock generator, the first prohibition element, a pilot signal sensor, a comparison element, the second input is connected with the input of the synchronization clock unit and is the input of the signal from the communication channel} and the coincidence element, the output of which is connected to the prohibitory input of the first recording element This is a series connected phasing indicator and a cycle phasing trigger whose output is connected to the second input of a matching element, and a series connected cycle label generator, the first delay element, the second delay element, the affected cycle indicator, the second prohibition element and the integrator whose output is connected to the second trigger input of the cyclic formation, where the output of the comparison element is connected to the clock input of the affected indicator 5 5 Q 0 five cycles and to the reset input of the phasing indicator loop, the clock of which is connected to the output of the clock generator and to the control input of the generator of the loop marks, the output of which is connected to the integrator's clock input, and the output of the first delay element is connected to the information input of the second prohibition element, different that, in order to extend the functionality by providing an estimate of the variance and spectral width of the phase fluctuations, a mismatch detector, an extreme controller, a control unit and consequently, the connected delay lines, the pulse duration controller, the pulse train selector, the counter block and the computing block, the signal input of the delay line, the first input of the mismatch detector and the second input of the counter block are respectively connected to the clock output of the test signal sensor and with the output of the comparison element, the output of the pulse length regulator is connected to the second input of the mismatch detector, the output of which is connected to the second input of the select pa duration of the pulse series, the third input of the counter and to the input of extreme regulator whose output is connected to the control input of the delay line, and first and second outputs of the control unit are respectively connected to the third input of the duration of the pulse series of the selector and to the second input of the calculation block "