SU1674394A1 - Digital data communications fault factor estimator - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to reduce the measurement time by reducing the synchronization setup time. The device contains a control signal generator 1, detectors 2–4 errors, counters 5–9, accumulator 10, OR element 11, delay element 12, mismatch signal structure analyzer 13, reference signal generator 14, synchronization unit 15, interval selection block 16, decisive block 17 and block 18 display. The signal from the output of the analyzer 13 is fed to the input of block 15, making its adjustment in the direction opposite to the direction of synchronization synchronization, thereby reducing the time the device takes to synchronize. The apparatus of claim 2 is characterized by the performance of the analyzer 13. 1c. f-ly, 2 ill.

Description

The device is related to communication technology and can be used to build test equipment for digital transmission systems.

The purpose of the invention is to reduce the measurement time by reducing the installation time synchronization

Fig. 1 is a block diagram of a device for measuring the error rate in digital information transmission paths. Fig. 2 is a block diagram of a signal structure analyzer.

SRI.

The device contains (FIG. 1) pilot signal generator 1, detectors 2 4 errors, counters 5 9 drive 10 element OR 11, delay time 12, analyzer 13 structure of the mismatch signal, generator 14 of the reference signal synchronization unit 15 block 16 ingress selection chopper block 17 and display unit 18 Analyzer 13 of the signal structure of the mismatch content; kig (Fig. 2) comparison units 19 21, elements OR 22 and 23. Counters 24 2B decoders 27-29, elements AND 30 32 elements HF 33 and 34 and generator 35 Chisrl

The device works as follows.

The operator 1 of the control signal (FIG. 1) generates, in accordance with the frequency of the test signal of a known structure. When this signal passes tp 3, the system under study (or cant / ti) has errors in it (the signal). At the receiving side, the generator 14 of the reference signal generates the signal is identical to the test synchronization unit 15 combines these signals at the input of the detector 2

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phase errors, while at the output of the error detector 2, an error stream (mismatch signal) is formed by elementwise comparison of the reference and control signals. The delay element 12 generates two signals that are identical to the reference one, but are shifted respectively with respect to the control one in the synchronization interval of the device by one and two clocks. Thus, the error detector 2 receives a reference signal, which is ahead of one clock signal received from the communication channel, and the detector 4 receives a similar reference signal that is delayed relative to the control signal by one clock cycle. The delay element 12 can be performed, in particular, on the shift register with a capacity of three bits.

The mismatch signal from the output of the 2 error detector (in the sync interval, the true mismatch signal) goes to the interval selection block 16, where it is divided into blocks of m elements. The signal from the output of the interval selection block 16 is fed to the counter 5, where the transmitted symbols (or blocks, which is not significant) are counted, which correspond to the operation of the device in terms of maintaining synchronism. In addition, the mismatch signal (error stream) is fed to the drive 10 and recorded therein. For example, the shift register can also act as a storage ring.

The signals from the three detectors 2-4 are fed to the corresponding counters 7-9, where the current number of errors is recorded. When the device is synchronized, the probability of an error at the output of detector 2 is equal (with sufficient accuracy) to the probability of an error in the system under study (communication channel). Usually this value, even for bad channels, does not exceed 1 GD2. At the same time, the probability of an error occurring at the outputs of the detectors 3 and 4 is approximately 0.5. At the moments of the end of the next block formed by the interval selection block 16, every m clock cycles in the analyzer 13 of the mismatch signal structure, the contents of counters 7, 8 and 9 are analyzed. Their contents are compared (Fig. 2) on comparison blocks 19-21 with the threshold code, formed on the generator 35. The value of this code is chosen so that the contents of the counters 7-9 in case of a synchronization failure exceed the value of the threshold code, and the contents of the same counter during synchronous operation of the device would be less than the threshold code. In the synchronous operation of the device at the moment when the permissive signal from block 16 arrives at comparison blocks 19-21 from the outputs of comparison blocks 19 and 21 (since they receive obviously large code values

counters 8 and 9, working in asynchronous channels), which are outputs of the type More, which indicates that the content-. mine of these counters is greater than the threshold code, signals are received for information

0 inputs of counters 24 and 26. From the first output of comparator block 20 (output of type More), the signal is not received, however, a signal is generated at its second output (output of type Less) and through the OR element 23 of the jam, generates a reset signal for counter 25 (Fig. 2 ), This happens at all times when the device is in synchronous mode.

If clock synchronization fails (as mentioned earlier, this is the main reason

0 device out of sync) the actual reference and reference signals are shifted relative to each other in the detector 2 errors per clock and now in the detector 2 the error probability

5 becomes 0.5. At the same time, in one of the remaining detectors 3 or 4 (since the shift occurs by one clock) both signals are in phase and the probability of error in the corresponding detector 3 or 4 becomes equal to the probability of an error in the communication channel, i.e., it drops sharply. Consider a specific variant of the device operation with such a clock synchronization failure, when the signal from generator 14 is

5, the fault is shifted in the direction of the lag relative to the control signal coming from the output of the system under study (communication channel).

In this case, the pilot signal does not coincide in phase with the input signal of detector 2, but becomes in-phase with the signal arriving at the other input of detector 3, previously ahead of the pilot signal.

5 When the signal arriving at the input of the detector 2 errors from the generator 14 and the control signal from the first output of the comparator block 20 is compared with the end of the next blocks of information

0 information pulses are received (More) to the information input of the counter 25. The counting module of this counter (counter 25) is chosen so that by the time the signal is generated from

The 5 outputs of the associated decoder 28 associated with the change in error statistics are transients in the three detector channels have ended (the minimum module of this counter is two, since a failure can occur in the middle of the block

information and only from the beginning of the next block the contents of counter 24 will be proportional to the probability of error in the communication channel). That is, the counter 25 is a damping or averaging device that improves the reliability of the detection of clock synchronization, and the distinction between error and packet error in the communication channel.

The decoder 28 is set to a code combination corresponding to the counter 25 counter module. Its operation (with the counter 25 counting module equal to K) via K blocks after synchronization failure causes the generation of a signal for polling the decoders 27 and 29 to AND 30 and 33 elements.

Counters 24 and 26 operate as follows. A More signal from the comparator adds one to the contents of the counter, and a Less signal resets the 24 and 2G counters to their original (zero) state. When a certain maximum state is reached, unlike counter 25, counters 24 and 26 remain in this state (with maximum content, regardless of the further arrival of information pulses at their information inputs. Decoders 27 and 29 are set to zero combination.

The enable signal from the decoder 28 causes a pulse to be formed at the output of that element 30 or 32, which is connected via the decoder 27 (29) to the counter 24 (26), which is currently in the zero state, and that counter is 24 or 2B which corresponds to the channel of the receiving part of the device inphasic with the control signal. In our example, when with the control signal the in-phase sequence arriving at the input of the 3 error detector, after the end of the block of information during which the synchronization failed, the contents of all tchikov 7-9 becomes larger than the threshold and the code for all the counters 24-26 receives a signal to increase its contents by one. After the information blocks, elements 30 and 32 are polled. Since synchronization fails, the signal of detector 3 becomes in-phase with the control number of errors becomes map and signals Less from the output of the comparison unit 19, the counter 24 is set to zero. The counter 26 at the same time is in a non-zero state, since the mismatching of the third channel relative to the pilot signal is two clocks. The signal g, the output of the first element And 30 through the element OR 22 analyzer

13 is fed to the input of block 1G of the city. carried out its adjustment in the opposite direction, the synchronization, that is, in our example, it forces it to issue an additional pulse to the input of the generator 14 with the reference signal and thereby shift its phase forward and eliminate the mismatch.

0 the signal becomes a signal arriving at the 2 error detector and the device is reset to the initial common-mode state

Similarly, testing of phasing takes place in case of advance of an additional signal compared to the control signal when clock synchronization fails. The only thing is that in this case the third to the control signal (with detector 4 and its associated circuits and blocks)

0 is given for lagging the generator 14.

If synchronization fails due to temporary signal loss (this happens much less frequently than

5, the shift of the signal file by one clock cycle) all the device clips are unsynchronized after generating a signal from the decoder 28 At the same time, signal C, de encoder 20 allows operation of the AND 31 element, at the output of which the signal appears and only when the second and third channels are non-phased with a control signal (there are no signals from AND 30 and 32 elements, signals from NA 33 and

5 34 According to the signal from element 31 through the second element OR 22 of the analyzer 13 in this case (the desired optimal direction of adjustment is unknown), a signal is generated, h is adjusted through a block 15 of synchronizing the generator 14 of the reference signal in one constant for the device, on the ground

When synchronization fails due to temporary (arbitrary time)

5, by the disappearance of a signal, the proposed device operates similarly to a prototype device.

The distinction between synchronization failure and error batch is achieved by selecting the interval

0 tons, along with the code and the counting module of the counter 25 of the analyzer 13. With the correct choice of these values, the error packet may trigger the comparison unit 20, but when analyzing subsequent blocks of information,

5 does not go out of sync, the first channel will generate signals to reset the counter 25 of the analyzer 13 and the device elements responsible for generating the adjustment signal will not trigger, starting with the decoder 28.

When detecting a synchronization failure (regardless of the cause), the signal from the analyzer 13 through the element OR 11 in the accumulator 10 erases the blocks corresponding to the interval in which the synchronization failure was detected (K + 1 blocks where the unit is added due to the block in which the failure occurred sync). At the same time, the signal from element OR 11 from the contents of counter 5 subtracts the number of pulses equal to K + 1 when they fix the number of data blocks (or m (K + 1) - when they fix the total number of transmitted pulses).

The signals from counters 6 and 5 enter the decision block 17, in which the error probability is determined as a ratio of the number of errors recorded by counter b, the total number of transmitted pulses recorded by counter 5. Display unit 18 displays the value of the error ratio.

It should be noted that when triggered in the event of a synchronization of the decoder 28 by a signal, it is reset to its original state through the OR 23 element counter 25 of the analyzer 13, with the help of which the device is ready after this point for further adjustment according to the same principle (if synphase not achieved).

In addition, the OR element 22 of the analyzer 13 can be connected to the AND element 32 by the second input, and to the element 32, thus changing the direction of the device adjustment in case of synchronization failure due to temporary signal loss (i.e. when the shift does not occur parcel, and on an unpredictable number of cycles and in an unpredictable direction).

In case of synchronization failure due to temporary signal loss, if the next adjustment does not lead to synchronization, the K + 1 data blocks are next erased and the adjustment continues according to the algorithm described above.

Claims (2)

1. Device for measuring the error rate in digital information transmission paths, comprising a first counter, serially connected pilot signal generator, error detector, interval selection unit, accumulator, second counter, decision unit and display unit, and serially connected discrepancy signal structure analyzer, synchronization unit and a reference signal generator, the output of the first counter is connected to another input of the decision block, characterized in that, for the purpose of reducing the measurement time by reducing the synchronization setup time; an OR element, a third counter, a second error detector connected in series, and a fourth counter, the output of which is connected to the first input of the mismatch signal structure analyzer, and a delayed serially connected element, a third error detector, and Fifth counter, the output of which is connected to the second input of the signal structure analyzer, the first output of which is connected to the first input of the OR element, and the second output is connected to the second input of the element 5 OR to another input of the synchronization unit, the third input is connected to the output of the third counter, and the fourth input is connected to the output of the interval selection block, to the first input of the first counter and to the combined second inputs of the third, fourth and fifth counters, the first input of the first detector error is combined with the first inputs of the second and third error detectors, the output of the first error detector is connected to the first input of the third counter and to the second input of the drive, the third input of which is connected to the output of the OR element and the second input the house of the first counter, the output of the reference signal generator is connected to 0 to the second input of the second error detector and to the input of the delay element, the second output of which is connected to the second input of the first error detector. 2. The device according to claim 1, distinguishing. 5, so that the discrepancy signal structure analyzer contains a serially connected number generator, the first comparison block, the first counter, the first decoder, the first AND element, the first element 0 NOT, the second element is AND, and the first element is OR, the other input of which is connected to the output of the first element AND, the second comparison unit connected in series, the second element OR, the second counter, the second decoder the third AND element and the second element NOT whose output is connected to the second the input of the second element And, the third input of which is connected to the output of the second decoder, serially connected third unit of comparison, the third counter and the third decoder, the output of which is connected to another input of the third element And, the output of the second unit Equal to the other input of the second counter, the output 5 of the second decoder is connected to other inputs of the first element AND and the second element OR, the output of the number generator is connected to the first inputs of the second and third comparison blocks, the first, second and third inputs of the signal structure analyzer the discrepancies are respectively with the output of the first element I, and the second is the second inputs of the first, third and second turns - the output of the third element I. of the comparison blocks, the first output is L. t11. Clock speed