SU450377A2 - Element Phasing Device for Discrete Signal Receivers - Google Patents

Description

The invention relates to the field of transmission of discrete information over communication channels.

A device for element-wise phasing of discrete-signal receivers is known, which contains an input device, a selector of lagging significant moments, a selector of leading significant moments, a frequency divider comparing the device, the master oscillator, a delay element for the duration of half of the work package, and a control element.

However, in the known device, when signals are received from the transmitter with a constant predominance exceeding 50%, stable false phasing with a fault of 180 ° is possible.

In this case, the “About the phasing system is not combined with the mathematical expectation of the deviations of the significant moments, but with the position that differs from it by an amount equal to 0.5. Where, then, is the duration of the ideal significant interval.

By "About the phasing device in the steady state" is understood the pulse formed by the element-by-phase phasing system, which corresponds to the moment of time that defines the boundary between the zones of delay and anticipation of significant moments. In a measuring instrument, this instant of time is taken as a reference point.

Thus, spurious phasing excludes reliable reception at receivers of discrete signals and reliable readout in measuring edge distortions.

In order to reduce the possibility of false phasing of discrete signal receivers 15 of the proposed device, the output of the input unit is connected to the auxiliary input of the frequency divider via the series-connected AND circuit, counting trigger and AND-IE circuit, in addition, two additional outputs of the input block are connected respectively to the setup input the counting trigger and to the prohibitory input of the circuit “NAND, the other two inputs of which are connected to the additional outputs of the frequency splitter, one of which is simultaneously connected to the control the input of the “I.

Pa figs. 1 shows a block diagram of the proposed element-wise phasing device; in fig. 2 - timing diagrams of the relative position of the pulses “On the phasing devices; in fig. 3 - timing diagrams of the operation of the control unit and the installation of the correct phasing.

For input signals with constant predominance exceeding 50% (Fig. 2, a), after establishing a stable state in the phasing system, two positions of the pulses "O device relative to the input signals" are possible. FIG. 2.6 shows the correct position of the pulses “O. With a predominance of 2a, the impulse "O device is separated by an amount (7 from the significant moments of different gender of the spaces. In Fig. 2, the wrong position of impulses" O is shown. With the same predominance of 2a impulse, "O is at a distance of 0.5 T and from significant moments of different polarities. With proper phasing, the number of pulses "O" that fit for a single unit interval of the input signal of any polarity (time point or tz-tz) is equal to a bullet or two. one significant pulse of the input signal is placed one pulse "O. The proposed device is based on the miscalculation of the number of pulses" O for the duration of a single significant interval. The proposed device contains (Fig. 1) input block 1, selector 2 of delayed significant moments, selector 3 of leading significant moments, frequency divider 4, comparing unit 5, master oscillator 6, delay element 7 for the duration of half of the working parcel, control element 8, as well as counting trigger 9, circuit "And 10, circuit" AND - NOT 11. Device work t as follows. Let some time after the signal was applied (Fig. 3, a) on the input unit 1, a steady state of the phasing system, corresponding to a false capture (Fig. 3.6), occurred. At time ti, a pulse from the input block corresponding to a significant moment establishes a counting trigger 9 at the set-up input to state I, prohibiting the input 12 from passing signals through the AND-NO circuit 11. From the same time until tz the signal input block permits the passage of pulses "O through the circuit" And 10 pa input counting trigger. In this case, until time iz, only one counting pulse arrives at the counting input of trigger 9. The trigger 9 is set to state II, allowing the passage of signals through the AND-NOT AND circuit on input 12. The input 13 of the AND-NOT circuit allows the signal to pass at the time. The impulse "O comes from frequency divider 4 to input 14 of the circuit" AND-NO 11. At input 15, the circuit is activated, AND-NOT 11 only when a significant interval, for: the duration of which the pulses are counted, "Oh, unit interval. Thus, when a pulse “O” is received in the time interval tz-t (time point h) to the circuit “NAND AND pulse from the output of the circuit (FIG. 3, d) sets the frequency divider to the position shifted relative to“ O by the value equal to 0.5 TO, which is equivalent to an instantaneous phase rotation of 180 °. Further phasing will be correct. Trigger 9 (Fig. 3b, c) changes its state two times in the time interval, i.e., prohibits the passage of signals through the AND-NE 11 circuit in the time interval 5-6. Thus, with the correct phasing, the pulses at the output of the circuit “AND-NO 11 are missing. The subject invention The device phased receivers of discrete signals by author. No. 267674, characterized in that,; In order to reduce the possibility of false fi-s ing, the output of the input unit is connected to the auxiliary input of the frequency divider via a serially connected circuit "AND, counted trigger and circuit" AND –NOT, in addition, two additional outputs of the input block are connected to the installation input of the counting trigger and to the prohibiting input of the circuit “NAND, to the other two inputs — of which additional outputs of a frequency divider are connected, one of which is simultaneously connected to the control input of the circuit“ I.

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